Lines Matching +full:reset +full:- +full:name
2 * QEMU model of the CRF - Clock Reset FPD.
5 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/misc/xlnx-zynqmp-crf.h"
17 #include "target/arm/arm-powerctl.h"
27 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; in ir_update_irq()
28 qemu_set_irq(s->irq_ir, pending); in ir_update_irq()
33 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_status_postw()
39 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_enable_prew()
42 s->regs[R_IR_MASK] &= ~val; in ir_enable_prew()
49 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in ir_disable_prew()
52 s->regs[R_IR_MASK] |= val; in ir_disable_prew()
59 XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque); in rst_fpd_apu_prew()
61 uint32_t val_old = s->regs[R_RST_FPD_APU]; in rst_fpd_apu_prew()
79 { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
80 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
83 },{ .name = "IR_MASK", .addr = A_IR_MASK,
84 .reset = 0x1,
86 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
88 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
90 },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
91 },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
92 .reset = 0x12c09,
94 },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
96 },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
98 },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
99 .reset = 0x2c09,
101 },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
103 },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
105 },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
106 .reset = 0x12809,
108 },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
110 },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
112 },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
113 .reset = 0x3f,
116 },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
117 .reset = 0x400,
119 },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
120 .reset = 0x400,
122 },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
123 .reset = 0x400,
125 },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
126 .reset = 0x3000400,
128 },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
129 .reset = 0x2500,
131 },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
132 .reset = 0x1002500,
134 },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
135 .reset = 0x1002300,
137 },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
138 .reset = 0x1032300,
140 },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
141 .reset = 0x1203200,
143 },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
144 .reset = 0x1000500,
146 },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
147 .reset = 0x1500,
149 },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
150 .reset = 0x1001600,
152 },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
153 .reset = 0x1500,
155 },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
156 .reset = 0x1000500,
158 },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
159 .reset = 0x1000500,
161 },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
162 .reset = 0x1000400,
164 },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
165 .reset = 0x1000800,
167 },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
168 .reset = 0xa00,
171 { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
172 .reset = 0xf9ffe,
174 },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
175 .reset = 0x3d0f,
178 },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
179 .reset = 0xf,
189 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in crf_reset_enter()
190 register_reset(&s->regs_info[i]); in crf_reset_enter()
215 s->reg_array = in crf_init()
218 s->regs_info, s->regs, in crf_init()
222 sysbus_init_mmio(sbd, &s->reg_array->mem); in crf_init()
223 sysbus_init_irq(sbd, &s->irq_ir); in crf_init()
229 register_finalize_block(s->reg_array); in crf_finalize()
233 .name = TYPE_XLNX_ZYNQMP_CRF,
247 dc->vmsd = &vmstate_crf; in crf_class_init()
248 rc->phases.enter = crf_reset_enter; in crf_class_init()
249 rc->phases.hold = crf_reset_hold; in crf_class_init()
253 .name = TYPE_XLNX_ZYNQMP_CRF,