Lines Matching +full:reset +full:- +full:name
2 * QEMU model of the Clock-Reset-LPD (CRL).
5 * SPDX-License-Identifier: GPL-2.0-or-later
15 #include "hw/qdev-properties.h"
21 #include "target/arm/arm-powerctl.h"
23 #include "hw/misc/xlnx-versal-crl.h"
31 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; in crl_update_irq()
32 qemu_set_irq(s->irq, pending); in crl_update_irq()
37 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_status_postw()
43 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_enable_prew()
46 s->regs[R_IR_MASK] &= ~val; in crl_enable_prew()
53 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_disable_prew()
56 s->regs[R_IR_MASK] |= val; in crl_disable_prew()
78 bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \
89 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_r5_prew()
91 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]); in crl_rst_r5_prew()
92 REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]); in crl_rst_r5_prew()
98 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_adma_prew()
101 /* A single register fans out to all ADMA reset inputs. */ in crl_rst_adma_prew()
102 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) { in crl_rst_adma_prew()
103 REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); in crl_rst_adma_prew()
110 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_uart0_prew()
112 REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); in crl_rst_uart0_prew()
118 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_uart1_prew()
120 REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); in crl_rst_uart1_prew()
126 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_gem0_prew()
128 REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); in crl_rst_gem0_prew()
134 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_gem1_prew()
136 REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); in crl_rst_gem1_prew()
142 XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque); in crl_rst_usb_prew()
144 REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); in crl_rst_usb_prew()
149 { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
150 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
153 },{ .name = "IR_MASK", .addr = A_IR_MASK,
154 .reset = 0x1,
156 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
158 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
160 },{ .name = "WPROT", .addr = A_WPROT,
161 },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
162 .reset = 0x1,
164 },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL,
165 .reset = 0x24809,
167 },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG,
168 .reset = 0x2000000,
170 },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG,
172 },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
173 .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
177 },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL,
178 .reset = 0x2000100,
180 },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL,
181 .reset = 0x6000300,
183 },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL,
184 .reset = 0x2000800,
186 },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL,
187 .reset = 0xe000300,
189 },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL,
190 .reset = 0x2000500,
192 },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL,
193 .reset = 0xe000a00,
195 },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL,
196 .reset = 0xe000a00,
198 },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL,
199 .reset = 0x300,
201 },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL,
202 .reset = 0x2001900,
204 },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL,
205 .reset = 0xc00,
207 },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL,
208 .reset = 0xc00,
210 },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL,
211 .reset = 0x600,
213 },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL,
214 .reset = 0x600,
216 },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL,
217 .reset = 0xc00,
219 },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL,
220 .reset = 0xc00,
222 },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL,
223 .reset = 0xc00,
225 },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL,
226 .reset = 0xc00,
228 },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL,
229 .reset = 0x300,
231 },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL,
232 .reset = 0x2000c00,
234 },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK,
235 },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL,
236 .reset = 0xf04,
238 },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
239 .reset = 0x300,
241 },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL,
242 .reset = 0x300,
244 },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL,
245 .reset = 0x3c00,
247 },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5,
248 .reset = 0x17,
251 },{ .name = "RST_ADMA", .addr = A_RST_ADMA,
252 .reset = 0x1,
254 },{ .name = "RST_GEM0", .addr = A_RST_GEM0,
255 .reset = 0x1,
257 },{ .name = "RST_GEM1", .addr = A_RST_GEM1,
258 .reset = 0x1,
260 },{ .name = "RST_SPARE", .addr = A_RST_SPARE,
261 .reset = 0x1,
262 },{ .name = "RST_USB0", .addr = A_RST_USB0,
263 .reset = 0x1,
265 },{ .name = "RST_UART0", .addr = A_RST_UART0,
266 .reset = 0x1,
268 },{ .name = "RST_UART1", .addr = A_RST_UART1,
269 .reset = 0x1,
271 },{ .name = "RST_SPI0", .addr = A_RST_SPI0,
272 .reset = 0x1,
273 },{ .name = "RST_SPI1", .addr = A_RST_SPI1,
274 .reset = 0x1,
275 },{ .name = "RST_CAN0", .addr = A_RST_CAN0,
276 .reset = 0x1,
277 },{ .name = "RST_CAN1", .addr = A_RST_CAN1,
278 .reset = 0x1,
279 },{ .name = "RST_I2C0", .addr = A_RST_I2C0,
280 .reset = 0x1,
281 },{ .name = "RST_I2C1", .addr = A_RST_I2C1,
282 .reset = 0x1,
283 },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD,
284 .reset = 0x33,
286 },{ .name = "RST_GPIO", .addr = A_RST_GPIO,
287 .reset = 0x1,
288 },{ .name = "RST_TTC", .addr = A_RST_TTC,
289 .reset = 0xf,
290 },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP,
291 .reset = 0x1,
292 },{ .name = "RST_SWDT", .addr = A_RST_SWDT,
293 .reset = 0x1,
294 },{ .name = "RST_OCM", .addr = A_RST_OCM,
295 },{ .name = "RST_IPI", .addr = A_RST_IPI,
296 },{ .name = "RST_FPD", .addr = A_RST_FPD,
297 .reset = 0x3,
298 },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE,
299 .reset = 0x1,
309 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { in crl_reset_enter()
310 register_reset(&s->regs_info[i]); in crl_reset_enter()
337 s->reg_array = in crl_init()
340 s->regs_info, s->regs, in crl_init()
344 sysbus_init_mmio(sbd, &s->reg_array->mem); in crl_init()
345 sysbus_init_irq(sbd, &s->irq); in crl_init()
347 for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { in crl_init()
349 (Object **)&s->cfg.cpu_r5[i], in crl_init()
354 for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { in crl_init()
356 (Object **)&s->cfg.adma[i], in crl_init()
361 for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { in crl_init()
363 (Object **)&s->cfg.uart[i], in crl_init()
368 for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { in crl_init()
370 (Object **)&s->cfg.gem[i], in crl_init()
376 (Object **)&s->cfg.gem[i], in crl_init()
384 register_finalize_block(s->reg_array); in crl_finalize()
388 .name = TYPE_XLNX_VERSAL_CRL,
402 dc->vmsd = &vmstate_crl; in crl_class_init()
404 rc->phases.enter = crl_reset_enter; in crl_class_init()
405 rc->phases.hold = crl_reset_hold; in crl_class_init()
409 .name = TYPE_XLNX_VERSAL_CRL,