hw/misc/npcm7xx_clk.c

201 static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)  in npcm7xx_clk_update_all_plls()
210 static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)  in npcm7xx_clk_update_all_sels()
219 static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)  in npcm7xx_clk_update_all_dividers()
228 static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)  in npcm7xx_clk_update_all_clocks()
638         NPCM7xxCLKState *clk, const PLLInitInfo *init_info)  in npcm7xx_init_clock_pll()
650         NPCM7xxCLKState *clk, const SELInitInfo *init_info)  in npcm7xx_init_clock_sel()
667         NPCM7xxCLKState *clk, const DividerInitInfo *init_info)  in npcm7xx_init_clock_divider()
686 static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,  in npcm7xx_get_clock()
703 static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)  in npcm7xx_connect_clocks()
730     NPCM7xxCLKState *s = opaque;  in npcm7xx_clk_read()
778     NPCM7xxCLKState *s = opaque;  in npcm7xx_clk_write()
845     NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque);  in npcm7xx_clk_perform_watchdog_reset()
872     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);  in npcm7xx_clk_enter_reset()
885 static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)  in npcm7xx_clk_init_clock_hierarchy()
923     NPCM7xxCLKState *s = NPCM7XX_CLK(obj);  in npcm7xx_clk_init()
933         NPCM7xxCLKState *clk = opaque;  in npcm7xx_clk_post_load()
944     NPCM7xxCLKState *s = NPCM7XX_CLK(dev);  in npcm7xx_clk_realize()
1005         VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
1006         VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
1007         VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
1076     .instance_size      = sizeof(NPCM7xxCLKState),