Lines Matching +full:sel +full:- +full:clk
21 #include "hw/qdev-clock.h"
23 #include "qemu/error-report.h"
38 #define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */
81 * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
111 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
114 #define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
117 #define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
124 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
129 freq = clock_get_hz(s->clock_in); in npcm7xx_clk_update_pll()
136 clock_update_hz(s->clock_out, freq); in npcm7xx_clk_update_pll()
142 uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset, in npcm7xx_clk_update_sel()
143 s->len); in npcm7xx_clk_update_sel()
145 if (index >= s->input_size) { in npcm7xx_clk_update_sel()
147 "%s: SEL index: %u out of range\n", in npcm7xx_clk_update_sel()
151 clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index])); in npcm7xx_clk_update_sel()
159 freq = s->divide(s); in npcm7xx_clk_update_divider()
160 clock_update_hz(s->clock_out, freq); in npcm7xx_clk_update_divider()
165 return clock_get_hz(s->clock_in) / s->divisor; in divide_by_constant()
170 return clock_get_hz(s->clock_in) / in divide_by_reg_divisor()
171 (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1); in divide_by_reg_divisor()
181 return clock_get_hz(s->clock_in) >> in shift_by_reg_divisor()
182 extract32(s->clk->regs[s->reg], s->offset, s->len); in shift_by_reg_divisor()
201 static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) in npcm7xx_clk_update_all_plls() argument
206 npcm7xx_clk_update_pll(&clk->plls[i]); in npcm7xx_clk_update_all_plls()
210 static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) in npcm7xx_clk_update_all_sels() argument
215 npcm7xx_clk_update_sel(&clk->sels[i]); in npcm7xx_clk_update_all_sels()
219 static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) in npcm7xx_clk_update_all_dividers() argument
224 npcm7xx_clk_update_divider(&clk->dividers[i]); in npcm7xx_clk_update_all_dividers()
228 static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) in npcm7xx_clk_update_all_clocks() argument
230 clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); in npcm7xx_clk_update_all_clocks()
231 npcm7xx_clk_update_all_plls(clk); in npcm7xx_clk_update_all_clocks()
232 npcm7xx_clk_update_all_sels(clk); in npcm7xx_clk_update_all_clocks()
233 npcm7xx_clk_update_all_dividers(clk); in npcm7xx_clk_update_all_clocks()
305 .public_name = "pixel-clock",
316 .public_name = "mc-phy-clock",
327 .public_name = "system-clock",
402 .name = "mc-divider",
407 .public_name = "mc-clock"
410 .name = "axi-divider",
420 .name = "ahb-divider",
430 .name = "ahb3-divider",
437 .public_name = "ahb3-spi3-clock"
440 .name = "spi0-divider",
447 .public_name = "spi0-clock",
450 .name = "spix-divider",
457 .public_name = "spix-clock",
460 .name = "apb1-divider",
467 .public_name = "apb1-clock",
470 .name = "apb2-divider",
477 .public_name = "apb2-clock",
480 .name = "apb3-divider",
487 .public_name = "apb3-clock",
490 .name = "apb4-divider",
497 .public_name = "apb4-clock",
500 .name = "apb5-divider",
507 .public_name = "apb5-clock",
510 .name = "clkout-divider",
520 .name = "uart-divider",
527 .public_name = "uart-clock",
530 .name = "timer-divider",
537 .public_name = "timer-clock",
540 .name = "adc-divider",
547 .public_name = "adc-clock",
550 .name = "mmc-divider",
557 .public_name = "mmc-clock",
560 .name = "sdhc-divider",
567 .public_name = "sdhc-clock",
570 .name = "gfxm-divider",
575 .public_name = "gfxm-clock",
578 .name = "utmi-divider",
585 .public_name = "utmi-clock",
598 pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in", in npcm7xx_clk_pll_init()
601 pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out"); in npcm7xx_clk_pll_init()
612 NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj); in npcm7xx_clk_sel_init() local
615 g_autofree char *s = g_strdup_printf("clock-in[%d]", i); in npcm7xx_clk_sel_init()
616 sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s, in npcm7xx_clk_sel_init()
617 npcm7xx_clk_update_sel_cb, sel, ClockUpdate); in npcm7xx_clk_sel_init()
619 sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out"); in npcm7xx_clk_sel_init()
631 div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in", in npcm7xx_clk_divider_init()
634 div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out"); in npcm7xx_clk_divider_init()
638 NPCM7xxCLKState *clk, const PLLInitInfo *init_info) in npcm7xx_init_clock_pll() argument
640 pll->name = init_info->name; in npcm7xx_init_clock_pll()
641 pll->clk = clk; in npcm7xx_init_clock_pll()
642 pll->reg = init_info->reg; in npcm7xx_init_clock_pll()
643 if (init_info->public_name != NULL) { in npcm7xx_init_clock_pll()
644 qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk), in npcm7xx_init_clock_pll()
645 init_info->public_name); in npcm7xx_init_clock_pll()
649 static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, in npcm7xx_init_clock_sel() argument
650 NPCM7xxCLKState *clk, const SELInitInfo *init_info) in npcm7xx_init_clock_sel() argument
652 int input_size = init_info->input_size; in npcm7xx_init_clock_sel()
654 sel->name = init_info->name; in npcm7xx_init_clock_sel()
655 sel->clk = clk; in npcm7xx_init_clock_sel()
656 sel->input_size = init_info->input_size; in npcm7xx_init_clock_sel()
658 sel->offset = init_info->offset; in npcm7xx_init_clock_sel()
659 sel->len = init_info->len; in npcm7xx_init_clock_sel()
660 if (init_info->public_name != NULL) { in npcm7xx_init_clock_sel()
661 qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk), in npcm7xx_init_clock_sel()
662 init_info->public_name); in npcm7xx_init_clock_sel()
667 NPCM7xxCLKState *clk, const DividerInitInfo *init_info) in npcm7xx_init_clock_divider() argument
669 div->name = init_info->name; in npcm7xx_init_clock_divider()
670 div->clk = clk; in npcm7xx_init_clock_divider()
672 div->divide = init_info->divide; in npcm7xx_init_clock_divider()
673 if (div->divide == divide_by_constant) { in npcm7xx_init_clock_divider()
674 div->divisor = init_info->divisor; in npcm7xx_init_clock_divider()
676 div->reg = init_info->reg; in npcm7xx_init_clock_divider()
677 div->offset = init_info->offset; in npcm7xx_init_clock_divider()
678 div->len = init_info->len; in npcm7xx_init_clock_divider()
680 if (init_info->public_name != NULL) { in npcm7xx_init_clock_divider()
681 qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk), in npcm7xx_init_clock_divider()
682 init_info->public_name); in npcm7xx_init_clock_divider()
686 static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, in npcm7xx_get_clock() argument
691 return clk->clkref; in npcm7xx_get_clock()
693 return clk->plls[index].clock_out; in npcm7xx_get_clock()
695 return clk->sels[index].clock_out; in npcm7xx_get_clock()
697 return clk->dividers[index].clock_out; in npcm7xx_get_clock()
703 static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) in npcm7xx_connect_clocks() argument
709 src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type, in npcm7xx_connect_clocks()
711 clock_set_source(clk->plls[i].clock_in, src); in npcm7xx_connect_clocks()
715 src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j], in npcm7xx_connect_clocks()
717 clock_set_source(clk->sels[i].clock_in[j], src); in npcm7xx_connect_clocks()
721 src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type, in npcm7xx_connect_clocks()
723 clock_set_source(clk->dividers[i].clock_in, src); in npcm7xx_connect_clocks()
744 "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n", in npcm7xx_clk_read()
750 value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND; in npcm7xx_clk_read()
761 value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ; in npcm7xx_clk_read()
765 value = s->regs[reg]; in npcm7xx_clk_read()
802 /* Power down -- clear lock and indicate loss of lock */ in npcm7xx_clk_write()
806 /* Normal mode -- assume always locked */ in npcm7xx_clk_write()
817 npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]); in npcm7xx_clk_write()
833 "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", in npcm7xx_clk_write()
838 s->regs[reg] = value; in npcm7xx_clk_write()
845 NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque); in npcm7xx_clk_perform_watchdog_reset() local
849 rcr = clk->regs[NPCM7XX_CLK_WD0RCR + n]; in npcm7xx_clk_perform_watchdog_reset()
874 QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); in npcm7xx_clk_enter_reset()
876 memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values)); in npcm7xx_clk_enter_reset()
877 s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in npcm7xx_clk_enter_reset()
889 s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL, 0); in npcm7xx_clk_init_clock_hierarchy()
898 &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL); in npcm7xx_clk_init_clock_hierarchy()
899 npcm7xx_init_clock_pll(&s->plls[i], s, in npcm7xx_clk_init_clock_hierarchy()
904 &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL); in npcm7xx_clk_init_clock_hierarchy()
905 npcm7xx_init_clock_sel(&s->sels[i], s, in npcm7xx_clk_init_clock_hierarchy()
910 &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER); in npcm7xx_clk_init_clock_hierarchy()
911 npcm7xx_init_clock_divider(&s->dividers[i], s, in npcm7xx_clk_init_clock_hierarchy()
918 clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); in npcm7xx_clk_init_clock_hierarchy()
925 memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, in npcm7xx_clk_init()
927 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); in npcm7xx_clk_init()
933 NPCM7xxCLKState *clk = opaque; in npcm7xx_clk_post_load() local
935 npcm7xx_clk_update_all_clocks(clk); in npcm7xx_clk_post_load()
952 if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) { in npcm7xx_clk_realize()
957 if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) { in npcm7xx_clk_realize()
962 if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) { in npcm7xx_clk_realize()
969 .name = "npcm7xx-clock-pll",
979 .name = "npcm7xx-clock-sel",
990 .name = "npcm7xx-clock-divider",
1000 .name = "npcm7xx-clk",
1016 dc->desc = "NPCM7xx Clock PLL Module"; in npcm7xx_clk_pll_class_init()
1017 dc->vmsd = &vmstate_npcm7xx_clk_pll; in npcm7xx_clk_pll_class_init()
1024 dc->desc = "NPCM7xx Clock SEL Module"; in npcm7xx_clk_sel_class_init()
1025 dc->vmsd = &vmstate_npcm7xx_clk_sel; in npcm7xx_clk_sel_class_init()
1032 dc->desc = "NPCM7xx Clock Divider Module"; in npcm7xx_clk_divider_class_init()
1033 dc->vmsd = &vmstate_npcm7xx_clk_divider; in npcm7xx_clk_divider_class_init()
1043 dc->desc = "NPCM7xx Clock Control Registers"; in npcm7xx_clk_class_init()
1044 dc->vmsd = &vmstate_npcm7xx_clk; in npcm7xx_clk_class_init()
1045 dc->realize = npcm7xx_clk_realize; in npcm7xx_clk_class_init()
1046 rc->phases.enter = npcm7xx_clk_enter_reset; in npcm7xx_clk_class_init()