hw/misc/exynos4210_pmu.c

68 /* Decides whether system-level low-power mode is used. */
70 /* Sets control options for CENTRAL_SEQ */
83 #define ADC_PHY_CONTROL          0x0718 /* TS-ADC control register */
84 #define PCIe_PHY_CONTROL         0x071C /* TS-PCIe control register */
85 #define SATA_PHY_CONTROL         0x0720 /* TS-SATA control register */
95 /* Registers to set system-level low-power option */
164 #define ARM_CORE0_OPTION        0x2008 /* Sets control options for ARM_CORE0 */
167 #define ARM_CORE1_OPTION        0x2088 /* Sets control options for ARM_CORE0 */
168 #define ARM_COMMON_OPTION       0x2408 /* Sets control options for ARM_COMMON */
175 /* Sets control options for PAD_RETENTION_MAUDIO */
177 /* Sets control options for PAD_RETENTION_GPIO */
179 /* Sets control options for PAD_RETENTION_UART */
181 /* Sets control options for PAD_RETENTION_MMCA */
183 /* Sets control options for PAD_RETENTION_MMCB */
185 /* Sets control options for PAD_RETENTION_EBIA */
187 /* Sets control options for PAD_RETENTION_EBIB */
192 /* Sets time required for XUSBXTI to be stabilized */
196 /* Sets time required for XXTI to be stabilized */
198 /* Sets time required for EXT_REGULATOR to be stabilized */
202 #define CAM_OPTION              0x3C08 /* Sets control options for CAM */
203 #define TV_CONFIGURATION        0x3C20 /* Configure power mode of TV */
204 #define TV_STATUS               0x3C24 /* Check power mode of TV */
205 #define TV_OPTION               0x3C28 /* Sets control options for TV */
208 #define MFC_OPTION              0x3C48 /* Sets control options for MFC */
211 #define G3D_OPTION              0x3C68 /* Sets control options for G3D */
214 #define LCD0_OPTION             0x3C88 /* Sets control options for LCD0 */
217 #define LCD1_OPTION             0x3CA8 /* Sets control options for LCD1 */
220 #define GPS_OPTION              0x3CE8 /* Sets control options for GPS */
223 #define GPS_ALIVE_OPTION        0x3D08 /* Sets control options for GPS */
421         if (reg_p->offset == offset) {  in exynos4210_pmu_read()
422             PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,  in exynos4210_pmu_read()
423                                    (uint32_t)offset, s->reg[i]);  in exynos4210_pmu_read()
424             return s->reg[i];  in exynos4210_pmu_read()
440         if (reg_p->offset == offset) {  in exynos4210_pmu_write()
441             PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,  in exynos4210_pmu_write()
443             s->reg[i] = val;  in exynos4210_pmu_write()
476         s->reg[i] = exynos4210_pmu_regs[i].reset_value;  in exynos4210_pmu_reset()
486     memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s,  in exynos4210_pmu_init()
488     sysbus_init_mmio(dev, &s->iomem);  in exynos4210_pmu_init()
506     dc->vmsd = &exynos4210_pmu_vmstate;  in exynos4210_pmu_class_init()