36     qemu_set_irq(s->irq, 0);  in mphi_lower_irq()
42     uint32_t val = 0;  in mphi_reg_read()
45     case 0x28:  /* outdda */  in mphi_reg_read()
48     case 0x2c:  /* outddb */  in mphi_reg_read()
51     case 0x4c:  /* ctrl */  in mphi_reg_read()
55     case 0x50:  /* intstat */  in mphi_reg_read()
58     case 0x1f0: /* swirq_set */  in mphi_reg_read()
61     case 0x1f4: /* swirq_clr */  in mphi_reg_read()
75     int do_irq = 0;  in mphi_reg_write()
78     case 0x28:  /* outdda */  in mphi_reg_write()
81     case 0x2c:  /* outddb */  in mphi_reg_write()
87     case 0x4c:  /* ctrl */  in mphi_reg_write()
93     case 0x50:  /* intstat */  in mphi_reg_write()
99     case 0x1f0: /* swirq_set */  in mphi_reg_write()
103     case 0x1f4: /* swirq_clr */  in mphi_reg_write()
112     if (do_irq > 0) {  in mphi_reg_write()
114     } else if (do_irq < 0) {  in mphi_reg_write()
131     s->outdda = 0;  in mphi_reset()
132     s->outddb = 0;  in mphi_reset()
133     s->ctrl = 0;  in mphi_reset()
134     s->intstat = 0;  in mphi_reset()
135     s->swirq = 0;  in mphi_reset()