Lines Matching +full:1 +full:ms
22 MachineState *ms = MACHINE(lvms); in create_fdt() local
25 ms->fdt = create_device_tree(&lvms->fdt_size); in create_fdt()
26 if (!ms->fdt) { in create_fdt()
28 exit(1); in create_fdt()
32 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", in create_fdt()
34 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); in create_fdt()
35 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); in create_fdt()
36 qemu_fdt_add_subnode(ms->fdt, "/chosen"); in create_fdt()
40 qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); in create_fdt()
46 MachineState *ms = MACHINE(lvms); in fdt_add_cpu_nodes() local
47 MachineClass *mc = MACHINE_GET_CLASS(ms); in fdt_add_cpu_nodes()
53 qemu_fdt_add_subnode(ms->fdt, "/cpus"); in fdt_add_cpu_nodes()
54 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); in fdt_add_cpu_nodes()
55 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
58 possible_cpus = mc->possible_cpu_arch_ids(ms); in fdt_add_cpu_nodes()
68 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_cpu_nodes()
69 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); in fdt_add_cpu_nodes()
70 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_cpu_nodes()
73 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", in fdt_add_cpu_nodes()
76 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); in fdt_add_cpu_nodes()
77 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", in fdt_add_cpu_nodes()
78 qemu_fdt_alloc_phandle(ms->fdt)); in fdt_add_cpu_nodes()
83 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); in fdt_add_cpu_nodes()
91 if (ms->smp.threads > 1) { in fdt_add_cpu_nodes()
94 num / (ms->smp.cores * ms->smp.threads), in fdt_add_cpu_nodes()
95 (num / ms->smp.threads) % ms->smp.cores, in fdt_add_cpu_nodes()
96 num % ms->smp.threads); in fdt_add_cpu_nodes()
100 num / ms->smp.cores, in fdt_add_cpu_nodes()
101 num % ms->smp.cores); in fdt_add_cpu_nodes()
103 qemu_fdt_add_path(ms->fdt, map_path); in fdt_add_cpu_nodes()
104 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", nodename); in fdt_add_cpu_nodes()
111 static void fdt_add_memory_node(MachineState *ms, in fdt_add_memory_node() argument
116 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_memory_node()
117 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base, in fdt_add_memory_node()
119 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); in fdt_add_memory_node()
121 if (ms->numa_state && ms->numa_state->num_nodes) { in fdt_add_memory_node()
122 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); in fdt_add_memory_node()
128 static void fdt_add_memory_nodes(MachineState *ms) in fdt_add_memory_nodes() argument
134 ram_size = ms->ram_size; in fdt_add_memory_nodes()
137 nodes = nb_numa_nodes = ms->numa_state->num_nodes; in fdt_add_memory_nodes()
138 numa_info = ms->numa_state->nodes; in fdt_add_memory_nodes()
140 nodes = 1; in fdt_add_memory_nodes()
156 fdt_add_memory_node(ms, base, gap, i); in fdt_add_memory_nodes()
163 fdt_add_memory_node(ms, base, size, i); in fdt_add_memory_nodes()
174 const MachineState *ms = MACHINE(lvms); in fdt_add_fw_cfg_node() local
177 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_fw_cfg_node()
178 qemu_fdt_setprop_string(ms->fdt, nodename, in fdt_add_fw_cfg_node()
180 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_fw_cfg_node()
182 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in fdt_add_fw_cfg_node()
188 MachineState *ms = MACHINE(lvms); in fdt_add_flash_node() local
202 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]); in fdt_add_flash_node()
207 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_flash_node()
208 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); in fdt_add_flash_node()
209 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_flash_node()
212 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); in fdt_add_flash_node()
219 MachineState *ms = MACHINE(lvms); in fdt_add_cpuic_node() local
222 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_cpuic_node()
224 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_cpuic_node()
225 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); in fdt_add_cpuic_node()
226 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_cpuic_node()
228 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_cpuic_node()
229 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); in fdt_add_cpuic_node()
237 MachineState *ms = MACHINE(lvms); in fdt_add_eiointc_node() local
242 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_eiointc_node()
244 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_eiointc_node()
245 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); in fdt_add_eiointc_node()
246 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_eiointc_node()
248 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_eiointc_node()
249 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); in fdt_add_eiointc_node()
250 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", in fdt_add_eiointc_node()
252 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); in fdt_add_eiointc_node()
253 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, in fdt_add_eiointc_node()
262 MachineState *ms = MACHINE(lvms); in fdt_add_pch_pic_node() local
267 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_pch_pic_node()
269 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_pch_pic_node()
270 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); in fdt_add_pch_pic_node()
271 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_pch_pic_node()
273 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, in fdt_add_pch_pic_node()
275 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_pch_pic_node()
276 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); in fdt_add_pch_pic_node()
277 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", in fdt_add_pch_pic_node()
279 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); in fdt_add_pch_pic_node()
287 MachineState *ms = MACHINE(lvms); in fdt_add_pch_msi_node() local
292 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_pch_msi_node()
294 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_pch_msi_node()
295 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); in fdt_add_pch_msi_node()
296 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_pch_msi_node()
298 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", in fdt_add_pch_msi_node()
301 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_pch_msi_node()
302 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", in fdt_add_pch_msi_node()
304 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", in fdt_add_pch_msi_node()
306 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", in fdt_add_pch_msi_node()
319 const MachineState *ms = MACHINE(lvms); in fdt_add_pcie_irq_map_node() local
343 irq_map[i] = cpu_to_be32(pin + 1); in fdt_add_pcie_irq_map_node()
344 i += 1; in fdt_add_pcie_irq_map_node()
358 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, in fdt_add_pcie_irq_map_node()
361 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", in fdt_add_pcie_irq_map_node()
377 const MachineState *ms = MACHINE(lvms); in fdt_add_pcie_node() local
380 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_pcie_node()
381 qemu_fdt_setprop_string(ms->fdt, nodename, in fdt_add_pcie_node()
383 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); in fdt_add_pcie_node()
384 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); in fdt_add_pcie_node()
385 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); in fdt_add_pcie_node()
386 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); in fdt_add_pcie_node()
387 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, in fdt_add_pcie_node()
388 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); in fdt_add_pcie_node()
389 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in fdt_add_pcie_node()
390 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_pcie_node()
392 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", in fdt_add_pcie_node()
393 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, in fdt_add_pcie_node()
395 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, in fdt_add_pcie_node()
397 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", in fdt_add_pcie_node()
409 MachineState *ms = MACHINE(lvms); in fdt_add_uart_node() local
412 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_uart_node()
413 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); in fdt_add_uart_node()
414 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); in fdt_add_uart_node()
415 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); in fdt_add_uart_node()
417 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); in fdt_add_uart_node()
419 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4); in fdt_add_uart_node()
420 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", in fdt_add_uart_node()
431 MachineState *ms = MACHINE(lvms); in fdt_add_rtc_node() local
434 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_rtc_node()
435 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_rtc_node()
437 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); in fdt_add_rtc_node()
438 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in fdt_add_rtc_node()
440 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", in fdt_add_rtc_node()
449 MachineState *ms = MACHINE(lvms); in fdt_add_ged_reset() local
453 ged_handle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_ged_reset()
455 qemu_fdt_add_subnode(ms->fdt, name); in fdt_add_ged_reset()
456 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon"); in fdt_add_ged_reset()
457 qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, base, 0x0, size); in fdt_add_ged_reset()
459 qemu_fdt_setprop_cell(ms->fdt, name, "reg-shift", 0); in fdt_add_ged_reset()
460 qemu_fdt_setprop_cell(ms->fdt, name, "reg-io-width", 1); in fdt_add_ged_reset()
461 qemu_fdt_setprop_cell(ms->fdt, name, "phandle", ged_handle); in fdt_add_ged_reset()
462 ged_handle = qemu_fdt_get_phandle(ms->fdt, name); in fdt_add_ged_reset()
466 qemu_fdt_add_subnode(ms->fdt, name); in fdt_add_ged_reset()
467 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); in fdt_add_ged_reset()
468 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle); in fdt_add_ged_reset()
469 qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_RESET); in fdt_add_ged_reset()
470 qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_RESET_VALUE); in fdt_add_ged_reset()
474 qemu_fdt_add_subnode(ms->fdt, name); in fdt_add_ged_reset()
475 qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); in fdt_add_ged_reset()
476 qemu_fdt_setprop_cell(ms->fdt, name, "regmap", ged_handle); in fdt_add_ged_reset()
477 qemu_fdt_setprop_cell(ms->fdt, name, "offset", ACPI_GED_REG_SLEEP_CTL); in fdt_add_ged_reset()
478 qemu_fdt_setprop_cell(ms->fdt, name, "value", ACPI_GED_SLP_EN | in fdt_add_ged_reset()
525 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer in virt_fdt_setup()
526 * access. FDT size limit with 1 MiB. in virt_fdt_setup()