Lines Matching +full:0 +full:x488
13 /* IC register offsets 0x0 - 0x400 */
14 #define CQ_SWI_CMD_HIST 0x020
15 #define CQ_SWI_CMD_POLL 0x028
16 #define CQ_SWI_CMD_BCAST 0x030
17 #define CQ_SWI_CMD_ASSIGN 0x038
18 #define CQ_SWI_CMD_BLK_UPD 0x040
19 #define CQ_SWI_RSP 0x048
20 #define CQ_CFG_PB_GEN 0x050
22 #define CQ_MSGSND 0x058
23 #define CQ_CNPM_SEL 0x078
24 #define CQ_IC_BAR 0x080
25 #define CQ_IC_BAR_VALID PPC_BIT(0)
27 #define CQ_TM1_BAR 0x90
28 #define CQ_TM2_BAR 0x0a0
29 #define CQ_TM_BAR_VALID PPC_BIT(0)
31 #define CQ_PC_BAR 0x0b0
32 #define CQ_PC_BAR_VALID PPC_BIT(0)
33 #define CQ_PC_BARM 0x0b8
35 #define CQ_VC_BAR 0x0c0
36 #define CQ_VC_BAR_VALID PPC_BIT(0)
37 #define CQ_VC_BARM 0x0c8
39 #define CQ_TAR 0x0f0
40 #define CQ_TAR_TBL_AUTOINC PPC_BIT(0)
47 #define CQ_TDR 0x0f8
48 #define CQ_TDR_VDT_VALID PPC_BIT(0)
51 #define CQ_TDR_EDT_TYPE PPC_BITMASK(0, 1)
52 #define CQ_TDR_EDT_INVALID 0
57 #define CQ_PBI_CTL 0x100
62 #define CQ_PBO_CTL 0x108
63 #define CQ_AIB_CTL 0x110
64 #define CQ_RST_CTL 0x118
65 #define CQ_FIRMASK 0x198
66 #define CQ_FIRMASK_AND 0x1a0
67 #define CQ_FIRMASK_OR 0x1a8
69 /* PC LBS1 register offsets 0x400 - 0x800 */
70 #define PC_TCTXT_CFG 0x400
71 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0)
79 #define PC_TCTXT_TRACK 0x408
80 #define PC_TCTXT_TRACK_EN PPC_BIT(0)
81 #define PC_TCTXT_INDIR0 0x420
82 #define PC_TCTXT_INDIR_VALID PPC_BIT(0)
84 #define PC_TCTXT_INDIR1 0x428
85 #define PC_TCTXT_INDIR2 0x430
86 #define PC_TCTXT_INDIR3 0x438
87 #define PC_THREAD_EN_REG0 0x440
88 #define PC_THREAD_EN_REG0_SET 0x448
89 #define PC_THREAD_EN_REG0_CLR 0x450
90 #define PC_THREAD_EN_REG1 0x460
91 #define PC_THREAD_EN_REG1_SET 0x468
92 #define PC_THREAD_EN_REG1_CLR 0x470
93 #define PC_GLOBAL_CONFIG 0x480
97 #define PC_VSD_TABLE_ADDR 0x488
98 #define PC_VSD_TABLE_DATA 0x490
99 #define PC_AT_KILL 0x4b0
100 #define PC_AT_KILL_VALID PPC_BIT(0)
103 #define PC_AT_KILL_MASK 0x4b8
106 #define PC_VPC_CACHE_ENABLE 0x708
107 #define PC_VPC_CACHE_EN_MASK PPC_BITMASK(0, 31)
108 #define PC_VPC_SCRUB_TRIG 0x710
109 #define PC_VPC_SCRUB_MASK 0x718
110 #define PC_SCRUB_VALID PPC_BIT(0)
115 #define PC_VPC_CWATCH_SPEC 0x738
116 #define PC_VPC_CWATCH_CONFLICT PPC_BIT(0)
120 #define PC_VPC_CWATCH_DAT0 0x740
121 #define PC_VPC_CWATCH_DAT1 0x748
122 #define PC_VPC_CWATCH_DAT2 0x750
123 #define PC_VPC_CWATCH_DAT3 0x758
124 #define PC_VPC_CWATCH_DAT4 0x760
125 #define PC_VPC_CWATCH_DAT5 0x768
126 #define PC_VPC_CWATCH_DAT6 0x770
127 #define PC_VPC_CWATCH_DAT7 0x778
129 /* VC0 register offsets 0x800 - 0xFFF */
130 #define VC_GLOBAL_CONFIG 0x800
132 #define VC_VSD_TABLE_ADDR 0x808
133 #define VC_VSD_TABLE_DATA 0x810
134 #define VC_IVE_ISB_BLOCK_MODE 0x818
135 #define VC_EQD_BLOCK_MODE 0x820
136 #define VC_VPS_BLOCK_MODE 0x828
137 #define VC_IRQ_CONFIG_IPI 0x840
140 #define VC_IRQ_CONFIG_HW 0x848
141 #define VC_IRQ_CONFIG_CASCADE1 0x850
142 #define VC_IRQ_CONFIG_CASCADE2 0x858
143 #define VC_IRQ_CONFIG_REDIST 0x860
144 #define VC_IRQ_CONFIG_IPI_CASC 0x868
146 #define VC_AIB_TX_ORDER_TAG2 0x890
147 #define VC_AT_MACRO_KILL 0x8b0
148 #define VC_AT_MACRO_KILL_MASK 0x8b8
149 #define VC_KILL_VALID PPC_BIT(0)
151 #define VC_KILL_IRQ 0
157 #define VC_EQC_CACHE_ENABLE 0x908
158 #define VC_EQC_CACHE_EN_MASK PPC_BITMASK(0, 15)
159 #define VC_EQC_SCRUB_TRIG 0x910
160 #define VC_EQC_SCRUB_MASK 0x918
161 #define VC_EQC_CONFIG 0x920
162 #define X_VC_EQC_CONFIG 0x214 /* XSCOM register */
174 #define VC_EQC_CWATCH_SPEC 0x928
175 #define VC_EQC_CWATCH_CONFLICT PPC_BIT(0)
179 #define VC_EQC_CWATCH_DAT0 0x930
180 #define VC_EQC_CWATCH_DAT1 0x938
181 #define VC_EQC_CWATCH_DAT2 0x940
182 #define VC_EQC_CWATCH_DAT3 0x948
183 #define VC_IVC_SCRUB_TRIG 0x990
184 #define VC_IVC_SCRUB_MASK 0x998
185 #define VC_SBC_SCRUB_TRIG 0xa10
186 #define VC_SBC_SCRUB_MASK 0xa18
187 #define VC_SCRUB_VALID PPC_BIT(0)
192 #define VC_IVC_CACHE_ENABLE 0x988
193 #define VC_IVC_CACHE_EN_MASK PPC_BITMASK(0, 15)
194 #define VC_SBC_CACHE_ENABLE 0xa08
195 #define VC_SBC_CACHE_EN_MASK PPC_BITMASK(0, 15)
196 #define VC_IVC_CACHE_SCRUB_TRIG 0x990
197 #define VC_IVC_CACHE_SCRUB_MASK 0x998
198 #define VC_SBC_CACHE_ENABLE 0xa08
199 #define VC_SBC_CACHE_SCRUB_TRIG 0xa10
200 #define VC_SBC_CACHE_SCRUB_MASK 0xa18
201 #define VC_SBC_CONFIG 0xa20
209 #define VST_ADDR_AUTOINC PPC_BIT(0)
211 #define VST_TSEL_IVT 0
230 #define VSD_MODE PPC_BITMASK(0, 1)
231 #define VSD_MODE_INVALID 0
235 #define VSD_ADDRESS_MASK 0x0ffffffffffff000ull