Lines Matching +full:0 +full:x430
18 #define X_CQ_XIVE_CAP 0x02
19 #define CQ_XIVE_CAP 0x010
20 #define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3)
23 #define CQ_XIVE_CAP_USER_INT_PRIO_1 0
28 #define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0
41 #define X_CQ_XIVE_CFG 0x03
42 #define CQ_XIVE_CFG 0x018
44 /* 0:7 reserved */
47 #define CQ_XIVE_CFG_INT_PRIO_1 0
52 #define CQ_XIVE_CFG_BLOCK_ID_4BITS 0
57 #define CQ_XIVE_CFG_THREADID_7BITS 0
66 #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
67 #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
69 #define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */
70 #define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */
73 #define X_CQ_IC_BAR 0x08
74 #define CQ_IC_BAR 0x040
75 #define CQ_IC_BAR_VALID PPC_BIT(0)
82 #define X_CQ_TM_BAR 0x09
83 #define CQ_TM_BAR 0x048
84 #define CQ_TM_BAR_VALID PPC_BIT(0)
89 #define X_CQ_ESB_BAR 0x0A
90 #define CQ_ESB_BAR 0x050
91 #define CQ_BAR_VALID PPC_BIT(0)
97 /* 0 (16M) - 16 (16T) */
100 #define X_CQ_END_BAR 0x0B
101 #define CQ_END_BAR 0x058
104 #define X_CQ_NVPG_BAR 0x0C
105 #define CQ_NVPG_BAR 0x060
108 #define X_CQ_NVC_BAR 0x0D
109 #define CQ_NVC_BAR 0x068
112 #define X_CQ_TAR 0x0E
113 #define CQ_TAR 0x070
114 #define CQ_TAR_AUTOINC PPC_BIT(0)
116 #define CQ_TAR_ESB 0 /* 0 - 15 */
117 #define CQ_TAR_END 2 /* 0 - 15 */
118 #define CQ_TAR_NVPG 3 /* 0 - 15 */
119 #define CQ_TAR_NVC 5 /* 0 - 15 */
123 #define X_CQ_TDR 0x0F
124 #define CQ_TDR 0x078
126 #define CQ_TDR_VALID PPC_BIT(0)
134 #define X_CQ_MSGSND 0x10
135 #define CQ_MSGSND 0x080
138 #define X_CQ_RST_CTL 0x12
139 #define CQ_RST_CTL 0x090
140 #define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */
147 #define X_CQ_CFG_PB_GEN 0x14
148 #define CQ_CFG_PB_GEN 0x0A0
156 #define X_CQ_FIR 0x30
157 #define X_CQ_FIR_AND 0x31
158 #define X_CQ_FIR_OR 0x32
159 #define CQ_FIR 0x180
160 #define CQ_FIR_AND 0x188
161 #define CQ_FIR_OR 0x190
170 #define X_CQ_FIRMASK 0x33
171 #define X_CQ_FIRMASK_AND 0x34
172 #define X_CQ_FIRMASK_OR 0x35
173 #define CQ_FIRMASK 0x198
174 #define CQ_FIRMASK_AND 0x1A0
175 #define CQ_FIRMASK_OR 0x1A8
182 #define X_VC_VSD_TABLE_ADDR 0x100
183 #define VC_VSD_TABLE_ADDR 0x000
184 #define VC_VSD_TABLE_AUTOINC PPC_BIT(0)
189 #define X_VC_VSD_TABLE_DATA 0x101
190 #define VC_VSD_TABLE_DATA 0x008
193 #define X_VC_AT_MACRO_KILL 0x102
194 #define VC_AT_MACRO_KILL 0x010
195 #define VC_AT_MACRO_KILL_VALID PPC_BIT(0)
201 #define X_VC_AT_MACRO_KILL_MASK 0x103
202 #define VC_AT_MACRO_KILL_MASK 0x018
204 /* Remote IRQs and ERQs configuration [n] (n = 0:6) */
205 #define X_VC_QUEUES_CFG_REM0 0x117
207 #define VC_QUEUES_CFG_REM0 0x0B8
208 #define VC_QUEUES_CFG_REM1 0x0C0
209 #define VC_QUEUES_CFG_REM2 0x0C8
210 #define VC_QUEUES_CFG_REM3 0x0D0
211 #define VC_QUEUES_CFG_REM4 0x0D8
212 #define VC_QUEUES_CFG_REM5 0x0E0
213 #define VC_QUEUES_CFG_REM6 0x0E8
222 #define X_VC_ESBC_FLUSH_CTRL 0x140
223 #define VC_ESBC_FLUSH_CTRL 0x200
224 #define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
228 #define X_VC_ESBC_FLUSH_POLL 0x141
229 #define VC_ESBC_FLUSH_POLL 0x208
230 #define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
236 #define X_VC_ESBC_FLUSH_INJECT 0x142
237 #define VC_ESBC_FLUSH_INJECT 0x210
240 #define X_VC_ESBC_CFG 0x148
241 #define VC_ESBC_CFG 0x240
244 #define X_VC_EASC_FLUSH_CTRL 0x160
245 #define VC_EASC_FLUSH_CTRL 0x300
246 #define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
250 #define X_VC_EASC_FLUSH_POLL 0x161
251 #define VC_EASC_FLUSH_POLL 0x308
252 #define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
258 #define X_VC_EASC_FLUSH_INJECT 0x162
259 #define VC_EASC_FLUSH_INJECT 0x310
266 #define X_VC_ENDC_FLUSH_CTRL 0x180
267 #define VC_ENDC_FLUSH_CTRL 0x400
268 #define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
274 #define X_VC_ENDC_FLUSH_POLL 0x181
275 #define VC_ENDC_FLUSH_POLL 0x408
282 #define X_VC_ENDC_FLUSH_INJECT 0x182
283 #define VC_ENDC_FLUSH_INJECT 0x410
286 #define X_VC_ENDC_SYNC_DONE 0x184
287 #define VC_ENDC_SYNC_DONE 0x420
288 #define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6)
289 #define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0)
299 #define X_VC_ENDC_WATCH_ASSIGN 0x186
300 #define VC_ENDC_WATCH_ASSIGN 0x430
303 #define X_VC_ENDC_CFG 0x188
304 #define VC_ENDC_CFG 0x440
307 /* ENDC cache watch specification 0 */
308 #define X_VC_ENDC_WATCH0_SPEC 0x1A0
309 #define VC_ENDC_WATCH0_SPEC 0x500
310 #define VC_ENDC_WATCH_CONFLICT PPC_BIT(0)
315 /* ENDC cache watch data 0 */
316 #define X_VC_ENDC_WATCH0_DATA0 0x1A4
317 #define X_VC_ENDC_WATCH0_DATA1 0x1A5
318 #define X_VC_ENDC_WATCH0_DATA2 0x1A6
319 #define X_VC_ENDC_WATCH0_DATA3 0x1A7
321 #define VC_ENDC_WATCH0_DATA0 0x520
322 #define VC_ENDC_WATCH0_DATA1 0x528
323 #define VC_ENDC_WATCH0_DATA2 0x530
324 #define VC_ENDC_WATCH0_DATA3 0x538
327 #define X_VC_ENDC_WATCH1_SPEC 0x1A8
328 #define VC_ENDC_WATCH1_SPEC 0x540
329 #define X_VC_ENDC_WATCH1_DATA0 0x1AC
330 #define X_VC_ENDC_WATCH1_DATA1 0x1AD
331 #define X_VC_ENDC_WATCH1_DATA2 0x1AE
332 #define X_VC_ENDC_WATCH1_DATA3 0x1AF
333 #define VC_ENDC_WATCH1_DATA0 0x560
334 #define VC_ENDC_WATCH1_DATA1 0x568
335 #define VC_ENDC_WATCH1_DATA2 0x570
336 #define VC_ENDC_WATCH1_DATA3 0x578
339 #define X_VC_ENDC_WATCH2_SPEC 0x1B0
340 #define VC_ENDC_WATCH2_SPEC 0x580
341 #define X_VC_ENDC_WATCH2_DATA0 0x1B4
342 #define X_VC_ENDC_WATCH2_DATA1 0x1B5
343 #define X_VC_ENDC_WATCH2_DATA2 0x1B6
344 #define X_VC_ENDC_WATCH2_DATA3 0x1B7
345 #define VC_ENDC_WATCH2_DATA0 0x5A0
346 #define VC_ENDC_WATCH2_DATA1 0x5A8
347 #define VC_ENDC_WATCH2_DATA2 0x5B0
348 #define VC_ENDC_WATCH2_DATA3 0x5B8
351 #define X_VC_ENDC_WATCH3_SPEC 0x1B8
352 #define VC_ENDC_WATCH3_SPEC 0x5C0
353 #define X_VC_ENDC_WATCH3_DATA0 0x1BC
354 #define X_VC_ENDC_WATCH3_DATA1 0x1BD
355 #define X_VC_ENDC_WATCH3_DATA2 0x1BE
356 #define X_VC_ENDC_WATCH3_DATA3 0x1BF
357 #define VC_ENDC_WATCH3_DATA0 0x5E0
358 #define VC_ENDC_WATCH3_DATA1 0x5E8
359 #define VC_ENDC_WATCH3_DATA2 0x5F0
360 #define VC_ENDC_WATCH3_DATA3 0x5F8
367 #define X_PC_VSD_TABLE_ADDR 0x200
368 #define PC_VSD_TABLE_ADDR 0x000
369 #define PC_VSD_TABLE_AUTOINC PPC_BIT(0)
374 #define X_PC_VSD_TABLE_DATA 0x201
375 #define PC_VSD_TABLE_DATA 0x008
378 #define X_PC_AT_KILL 0x202
379 #define PC_AT_KILL 0x010
380 #define PC_AT_KILL_VALID PPC_BIT(0)
387 #define X_PC_AT_KILL_MASK 0x203
388 #define PC_AT_KILL_MASK 0x018
398 #define X_PC_NXC_FLUSH_CTRL 0x280
399 #define PC_NXC_FLUSH_CTRL 0x400
400 #define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
406 #define X_PC_NXC_FLUSH_POLL 0x281
407 #define PC_NXC_FLUSH_POLL 0x408
409 #define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0
414 #define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35) /* 0: Ign */
419 #define X_PC_NXC_FLUSH_INJECT 0x282
420 #define PC_NXC_FLUSH_INJECT 0x410
423 #define X_PC_NXC_WATCH_ASSIGN 0x286
424 #define PC_NXC_WATCH_ASSIGN 0x430
427 #define X_PC_NXC_PROC_CONFIG 0x28A
428 #define PC_NXC_PROC_CONFIG 0x450
429 #define PC_NXC_PROC_CONFIG_WATCH_ASSIGN PPC_BITMASK(0, 3)
433 /* NxC Cache Watch 0 Specification */
434 #define X_PC_NXC_WATCH0_SPEC 0x2A0
435 #define PC_NXC_WATCH0_SPEC 0x500
436 #define PC_NXC_WATCH_CONFLICT PPC_BIT(0)
439 #define PC_NXC_WATCH_NXC_NVP 0
445 /* NxC Cache Watch 0 Data */
446 #define X_PC_NXC_WATCH0_DATA0 0x2A4
447 #define X_PC_NXC_WATCH0_DATA1 0x2A5
448 #define X_PC_NXC_WATCH0_DATA2 0x2A6
449 #define X_PC_NXC_WATCH0_DATA3 0x2A7
451 #define PC_NXC_WATCH0_DATA0 0x520
452 #define PC_NXC_WATCH0_DATA1 0x528
453 #define PC_NXC_WATCH0_DATA2 0x530
454 #define PC_NXC_WATCH0_DATA3 0x538
457 #define X_PC_NXC_WATCH1_SPEC 0x2A8
458 #define PC_NXC_WATCH1_SPEC 0x540
459 #define X_PC_NXC_WATCH1_DATA0 0x2AC
460 #define X_PC_NXC_WATCH1_DATA1 0x2AD
461 #define X_PC_NXC_WATCH1_DATA2 0x2AE
462 #define X_PC_NXC_WATCH1_DATA3 0x2AF
463 #define PC_NXC_WATCH1_DATA0 0x560
464 #define PC_NXC_WATCH1_DATA1 0x568
465 #define PC_NXC_WATCH1_DATA2 0x570
466 #define PC_NXC_WATCH1_DATA3 0x578
469 #define X_PC_NXC_WATCH2_SPEC 0x2B0
470 #define PC_NXC_WATCH2_SPEC 0x580
471 #define X_PC_NXC_WATCH2_DATA0 0x2B4
472 #define X_PC_NXC_WATCH2_DATA1 0x2B5
473 #define X_PC_NXC_WATCH2_DATA2 0x2B6
474 #define X_PC_NXC_WATCH2_DATA3 0x2B7
475 #define PC_NXC_WATCH2_DATA0 0x5A0
476 #define PC_NXC_WATCH2_DATA1 0x5A8
477 #define PC_NXC_WATCH2_DATA2 0x5B0
478 #define PC_NXC_WATCH2_DATA3 0x5B8
481 #define X_PC_NXC_WATCH3_SPEC 0x2B8
482 #define PC_NXC_WATCH3_SPEC 0x5C0
483 #define X_PC_NXC_WATCH3_DATA0 0x2BC
484 #define X_PC_NXC_WATCH3_DATA1 0x2BD
485 #define X_PC_NXC_WATCH3_DATA2 0x2BE
486 #define X_PC_NXC_WATCH3_DATA3 0x2BF
487 #define PC_NXC_WATCH3_DATA0 0x5E0
488 #define PC_NXC_WATCH3_DATA1 0x5E8
489 #define PC_NXC_WATCH3_DATA2 0x5F0
490 #define PC_NXC_WATCH3_DATA3 0x5F8
497 #define X_TCTXT_EN0 0x300
498 #define TCTXT_EN0 0x000
501 #define X_TCTXT_EN0_SET 0x302
502 #define TCTXT_EN0_SET 0x010
505 #define X_TCTXT_EN0_RESET 0x303
506 #define TCTXT_EN0_RESET 0x018
509 #define X_TCTXT_EN1 0x304
510 #define TCTXT_EN1 0x020
513 #define X_TCTXT_EN1_SET 0x306
514 #define TCTXT_EN1_SET 0x030
517 #define X_TCTXT_EN1_RESET 0x307
518 #define TCTXT_EN1_RESET 0x038
521 #define X_TCTXT_CFG 0x328
522 #define TCTXT_CFG 0x140
527 #define VST_ESB 0
546 #define VSD_MODE PPC_BITMASK(0, 1)
553 #define VSD_ADDRESS_MASK 0x00fffffffffff000ull