Lines Matching +full:intc +full:- +full:nr +full:- +full:irqs
4 * Copyright (c) 2019-2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
25 #include "hw/qdev-properties.h"
71 * fifos of the VC sub-engine in case of overflow.
73 * 0 - IPI,
74 * 1 - HWD,
75 * 2 - NxC,
76 * 3 - INT,
77 * 4 - OS-Queue,
78 * 5 - Pool-Queue,
79 * 6 - Hard-Queue
85 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
86 (xive)->chip->chip_id, ## __VA_ARGS__);
93 uint8_t blk = xive->chip->chip_id; in pnv_xive2_block_id()
94 uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3]; in pnv_xive2_block_id()
114 for (i = 0; i < pnv->num_chips; i++) { in pnv_xive2_get_remote()
115 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); in pnv_xive2_get_remote()
116 PnvXive2 *xive = &chip10->xive; in pnv_xive2_get_remote()
149 idx_max = vst_tsize / info->size - 1; in pnv_xive2_vst_addr_direct()
153 info->name, idx, idx_max); in pnv_xive2_vst_addr_direct()
158 return vst_addr + idx * info->size; in pnv_xive2_vst_addr_direct()
176 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); in pnv_xive2_vst_addr_indirect()
184 xive2_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive2_vst_addr_indirect()
189 vst_per_page = (1ull << page_shift) / info->size; in pnv_xive2_vst_addr_indirect()
200 xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx); in pnv_xive2_vst_addr_indirect()
211 info->name, idx); in pnv_xive2_vst_addr_indirect()
222 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); in pnv_xive2_nvc_table_compress_shift()
229 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); in pnv_xive2_nvg_table_compress_shift()
239 if (blk >= info->max_blocks) { in pnv_xive2_vst_addr()
241 blk, info->name, idx); in pnv_xive2_vst_addr()
245 vsd = xive->vsds[type][blk]; in pnv_xive2_vst_addr()
248 blk, info->name, idx); in pnv_xive2_vst_addr()
280 return -1; in pnv_xive2_vst_read()
285 info->size); in pnv_xive2_vst_read()
288 " for VST %s %x/%x\n", addr, info->name, blk, idx); in pnv_xive2_vst_read()
289 return -1; in pnv_xive2_vst_read()
294 #define XIVE_VST_WORD_ALL -1
304 return -1; in pnv_xive2_vst_write()
310 info->size); in pnv_xive2_vst_write()
320 "for VST %s %x/%x\n", addr, info->name, blk, idx); in pnv_xive2_vst_write()
321 return -1; in pnv_xive2_vst_write()
333 return -1; in pnv_xive2_get_pq()
336 *pq = xive_source_esb_get(&xive->ipi_source, idx); in pnv_xive2_get_pq()
347 return -1; in pnv_xive2_set_pq()
350 *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq); in pnv_xive2_set_pq()
413 int ic_topo_id = xive->chip->chip_id; in pnv_xive2_inject_notify()
424 return -1; in pnv_xive2_inject_notify()
445 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()
446 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()
449 endc_watch[i] = cpu_to_be64(xive->vc_regs[data_reg + i]); in pnv_xive2_end_update()
467 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_cache_load()
468 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); in pnv_xive2_end_cache_load()
475 xive->vc_regs[data_reg + i] = be64_to_cpu(endc_watch[i]); in pnv_xive2_end_cache_load()
524 return -1; in pnv_xive2_nxc_to_table_type()
532 uint32_t idx, table_type = -1; in pnv_xive2_nxc_update()
540 nxc_type = GETFIELD(PC_NXC_WATCH_NXC_TYPE, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_update()
541 blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_update()
542 idx = GETFIELD(PC_NXC_WATCH_INDEX, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_update()
547 nxc_watch[i] = cpu_to_be64(xive->pc_regs[data_reg + i]); in pnv_xive2_nxc_update()
557 uint32_t idx, table_type = -1; in pnv_xive2_nxc_cache_load()
565 nxc_type = GETFIELD(PC_NXC_WATCH_NXC_TYPE, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_cache_load()
566 blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_cache_load()
567 idx = GETFIELD(PC_NXC_WATCH_INDEX, xive->pc_regs[spec_reg]); in pnv_xive2_nxc_cache_load()
577 xive->pc_regs[data_reg + i] = be64_to_cpu(nxc_watch[i]); in pnv_xive2_nxc_cache_load()
588 return -1; in pnv_xive2_get_eas()
599 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { in pnv_xive2_get_config()
603 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) { in pnv_xive2_get_config()
608 xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) { in pnv_xive2_get_config()
622 return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit); in pnv_xive2_is_cpu_enabled()
631 PnvChip *chip = xive->chip; in pnv_xive2_match_nvt()
635 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; in pnv_xive2_match_nvt()
637 for (i = 0; i < chip->nr_cores; i++) { in pnv_xive2_match_nvt()
638 PnvCore *pc = chip->cores[i]; in pnv_xive2_match_nvt()
641 for (j = 0; j < cc->nr_threads; j++) { in pnv_xive2_match_nvt()
642 PowerPCCPU *cpu = pc->threads[j]; in pnv_xive2_match_nvt()
650 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive2_match_nvt()
662 if (ring != -1) { in pnv_xive2_match_nvt()
664 * For VP-specific match, finding more than one is a in pnv_xive2_match_nvt()
667 if (!cam_ignore && match->tctx) { in pnv_xive2_match_nvt()
672 return -1; in pnv_xive2_match_nvt()
682 match->precluded = true; in pnv_xive2_match_nvt()
684 if (!match->tctx) { in pnv_xive2_match_nvt()
685 match->ring = ring; in pnv_xive2_match_nvt()
686 match->tctx = tctx; in pnv_xive2_match_nvt()
702 if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { in pnv_xive2_presenter_get_config()
713 PnvChip *chip = xive->chip; in pnv_xive2_broadcast()
716 xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; in pnv_xive2_broadcast()
718 for (i = 0; i < chip->nr_cores; i++) { in pnv_xive2_broadcast()
719 PnvCore *pc = chip->cores[i]; in pnv_xive2_broadcast()
722 for (j = 0; j < cc->nr_threads; j++) { in pnv_xive2_broadcast()
723 PowerPCCPU *cpu = pc->threads[j]; in pnv_xive2_broadcast()
731 tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive2_broadcast()
741 if (ring != -1) { in pnv_xive2_broadcast()
762 XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; in pnv_xive2_tm_get_xive()
792 uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]); in pnv_xive2_stt_set_data()
794 xive->cq_regs[CQ_TAR >> 3]); in pnv_xive2_stt_set_data()
801 xive->tables[tsel][entry] = val; in pnv_xive2_stt_set_data()
805 return -1; in pnv_xive2_stt_set_data()
808 if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) { in pnv_xive2_stt_set_data()
809 xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT, in pnv_xive2_stt_set_data()
810 xive->cq_regs[CQ_TAR >> 3], ++entry); in pnv_xive2_stt_set_data()
821 Xive2EndSource *end_xsrc = &xive->end_source; in pnv_xive2_vst_set_exclusive()
822 XiveSource *xsrc = &xive->ipi_source; in pnv_xive2_vst_set_exclusive()
832 xive2_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive2_vst_set_exclusive()
841 info->name, vst_addr, page_shift); in pnv_xive2_vst_set_exclusive()
846 xive->vsds[type][blk] = vsd; in pnv_xive2_vst_set_exclusive()
861 if (memory_region_is_mapped(&xsrc->esb_mmio)) { in pnv_xive2_vst_set_exclusive()
862 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); in pnv_xive2_vst_set_exclusive()
865 memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE in pnv_xive2_vst_set_exclusive()
866 * (1ull << xsrc->esb_shift)); in pnv_xive2_vst_set_exclusive()
869 memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio); in pnv_xive2_vst_set_exclusive()
879 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { in pnv_xive2_vst_set_exclusive()
880 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); in pnv_xive2_vst_set_exclusive()
883 memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size) in pnv_xive2_vst_set_exclusive()
884 * (1ull << end_xsrc->esb_shift)); in pnv_xive2_vst_set_exclusive()
886 memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio); in pnv_xive2_vst_set_exclusive()
903 * Both PC and VC sub-engines are configured as each use the Virtual
931 xive->vsds[type][blk] = vsd; in pnv_xive2_vst_set_data()
947 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_vc_vst_set_data()
949 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_vc_vst_set_data()
972 * Pages 10-255: Reserved
973 * Pages 256-383: Direct mapped Thread Context Area (reads & writes)
975 * Pages 384-511: Reserved
995 { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops },
996 { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops },
997 { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops },
998 { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops },
999 { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops },
1001 { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops },
1002 { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops },
1003 /* pages 10-255 reserved */
1004 { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops },
1005 /* pages 384-511 reserved */
1022 val = xive->cq_regs[reg]; in pnv_xive2_ic_cq_read()
1056 xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1058 xive->ic_base = 0; in pnv_xive2_ic_cq_write()
1059 if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) { in pnv_xive2_ic_cq_write()
1060 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { in pnv_xive2_ic_cq_write()
1061 memory_region_del_subregion(&xive->ic_mmio, in pnv_xive2_ic_cq_write()
1062 &xive->ic_mmios[i]); in pnv_xive2_ic_cq_write()
1064 memory_region_del_subregion(sysmem, &xive->ic_mmio); in pnv_xive2_ic_cq_write()
1067 xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K); in pnv_xive2_ic_cq_write()
1068 if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1069 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { in pnv_xive2_ic_cq_write()
1070 memory_region_add_subregion(&xive->ic_mmio, in pnv_xive2_ic_cq_write()
1071 pnv_xive2_ic_regions[i].pgoff << xive->ic_shift, in pnv_xive2_ic_cq_write()
1072 &xive->ic_mmios[i]); in pnv_xive2_ic_cq_write()
1074 memory_region_add_subregion(sysmem, xive->ic_base, in pnv_xive2_ic_cq_write()
1075 &xive->ic_mmio); in pnv_xive2_ic_cq_write()
1081 xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1083 xive->tm_base = 0; in pnv_xive2_ic_cq_write()
1084 if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) { in pnv_xive2_ic_cq_write()
1085 memory_region_del_subregion(sysmem, &xive->tm_mmio); in pnv_xive2_ic_cq_write()
1088 xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K); in pnv_xive2_ic_cq_write()
1089 if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1090 memory_region_add_subregion(sysmem, xive->tm_base, in pnv_xive2_ic_cq_write()
1091 &xive->tm_mmio); in pnv_xive2_ic_cq_write()
1097 xive->esb_shift = val & CQ_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1099 xive->esb_base = 0; in pnv_xive2_ic_cq_write()
1100 if (xive->cq_regs[reg] & CQ_BAR_VALID) { in pnv_xive2_ic_cq_write()
1101 memory_region_del_subregion(sysmem, &xive->esb_mmio); in pnv_xive2_ic_cq_write()
1104 xive->esb_base = val & CQ_BAR_ADDR; in pnv_xive2_ic_cq_write()
1105 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1106 memory_region_set_size(&xive->esb_mmio, in pnv_xive2_ic_cq_write()
1108 memory_region_add_subregion(sysmem, xive->esb_base, in pnv_xive2_ic_cq_write()
1109 &xive->esb_mmio); in pnv_xive2_ic_cq_write()
1115 xive->end_shift = val & CQ_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1117 xive->end_base = 0; in pnv_xive2_ic_cq_write()
1118 if (xive->cq_regs[reg] & CQ_BAR_VALID) { in pnv_xive2_ic_cq_write()
1119 memory_region_del_subregion(sysmem, &xive->end_mmio); in pnv_xive2_ic_cq_write()
1122 xive->end_base = val & CQ_BAR_ADDR; in pnv_xive2_ic_cq_write()
1123 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1124 memory_region_set_size(&xive->end_mmio, in pnv_xive2_ic_cq_write()
1126 memory_region_add_subregion(sysmem, xive->end_base, in pnv_xive2_ic_cq_write()
1127 &xive->end_mmio); in pnv_xive2_ic_cq_write()
1133 xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1135 xive->nvc_base = 0; in pnv_xive2_ic_cq_write()
1136 if (xive->cq_regs[reg] & CQ_BAR_VALID) { in pnv_xive2_ic_cq_write()
1137 memory_region_del_subregion(sysmem, &xive->nvc_mmio); in pnv_xive2_ic_cq_write()
1140 xive->nvc_base = val & CQ_BAR_ADDR; in pnv_xive2_ic_cq_write()
1141 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1142 memory_region_set_size(&xive->nvc_mmio, in pnv_xive2_ic_cq_write()
1144 memory_region_add_subregion(sysmem, xive->nvc_base, in pnv_xive2_ic_cq_write()
1145 &xive->nvc_mmio); in pnv_xive2_ic_cq_write()
1151 xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12; in pnv_xive2_ic_cq_write()
1153 xive->nvpg_base = 0; in pnv_xive2_ic_cq_write()
1154 if (xive->cq_regs[reg] & CQ_BAR_VALID) { in pnv_xive2_ic_cq_write()
1155 memory_region_del_subregion(sysmem, &xive->nvpg_mmio); in pnv_xive2_ic_cq_write()
1158 xive->nvpg_base = val & CQ_BAR_ADDR; in pnv_xive2_ic_cq_write()
1159 if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) { in pnv_xive2_ic_cq_write()
1160 memory_region_set_size(&xive->nvpg_mmio, in pnv_xive2_ic_cq_write()
1162 memory_region_add_subregion(sysmem, xive->nvpg_base, in pnv_xive2_ic_cq_write()
1163 &xive->nvpg_mmio); in pnv_xive2_ic_cq_write()
1180 xive->cq_regs[reg] = val; in pnv_xive2_ic_cq_write()
1203 for (i = 3; i >= 0; i--) { in pnv_xive2_cache_watch_assign()
1207 val = 3 - i; in pnv_xive2_cache_watch_assign()
1217 uint8_t engine_bit = 3 - watch_engine; in pnv_xive2_cache_watch_release()
1227 xive->vc_regs[VC_ENDC_CFG >> 3]); in pnv_xive2_endc_cache_watch_assign()
1228 uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3]; in pnv_xive2_endc_cache_watch_assign()
1240 xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state; in pnv_xive2_endc_cache_watch_assign()
1248 uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3]; in pnv_xive2_endc_cache_watch_release()
1251 xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state; in pnv_xive2_endc_cache_watch_release()
1268 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1275 xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_read()
1276 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1280 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1287 xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_read()
1288 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1296 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1306 watch_engine = (offset - VC_ENDC_WATCH0_SPEC) >> 6; in pnv_xive2_ic_vc_read()
1307 xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); in pnv_xive2_ic_vc_read()
1309 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1320 watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; in pnv_xive2_ic_vc_read()
1322 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1329 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1333 xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_read()
1334 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1341 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1345 xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID; in pnv_xive2_ic_vc_read()
1346 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1353 val = xive->vc_regs[reg]; in pnv_xive2_ic_vc_read()
1391 xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_write()
1407 xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_write()
1438 watch_engine = (offset - VC_ENDC_WATCH0_DATA0) >> 6; in pnv_xive2_ic_vc_write()
1439 xive->vc_regs[reg] = val; in pnv_xive2_ic_vc_write()
1446 xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_vc_write()
1477 xive->vc_regs[reg] = val; in pnv_xive2_ic_vc_write()
1497 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3]); in pnv_xive2_nxc_cache_watch_assign()
1498 uint64_t state = xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3]; in pnv_xive2_nxc_cache_watch_assign()
1510 xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3] = state; in pnv_xive2_nxc_cache_watch_assign()
1518 uint64_t state = xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3]; in pnv_xive2_nxc_cache_watch_release()
1521 xive->pc_regs[PC_NXC_WATCH_ASSIGN >> 3] = state; in pnv_xive2_nxc_cache_watch_release()
1528 uint64_t val = -1; in pnv_xive2_ic_pc_read()
1538 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1546 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1556 watch_engine = (offset - PC_NXC_WATCH0_SPEC) >> 6; in pnv_xive2_ic_pc_read()
1557 xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT); in pnv_xive2_ic_pc_read()
1559 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1570 watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6; in pnv_xive2_ic_pc_read()
1572 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1579 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1583 xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_pc_read()
1584 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1591 xive->pc_regs[reg] &= ~PC_AT_KILL_VALID; in pnv_xive2_ic_pc_read()
1592 val = xive->pc_regs[reg]; in pnv_xive2_ic_pc_read()
1605 xive->pc_regs[PC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_pc_vst_set_data()
1607 xive->pc_regs[PC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_pc_vst_set_data()
1623 * The Xive2Router model combines both VC and PC sub-engines. We in pnv_xive2_ic_pc_write()
1659 watch_engine = (offset - PC_NXC_WATCH0_DATA0) >> 6; in pnv_xive2_ic_pc_write()
1660 xive->pc_regs[reg] = val; in pnv_xive2_ic_pc_write()
1666 xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID; in pnv_xive2_ic_pc_write()
1685 xive->pc_regs[reg] = val; in pnv_xive2_ic_pc_write()
1707 uint64_t val = -1; in pnv_xive2_ic_tctxt_read()
1716 val = xive->tctxt_regs[reg]; in pnv_xive2_ic_tctxt_read()
1721 val = xive->tctxt_regs[TCTXT_EN0 >> 3]; in pnv_xive2_ic_tctxt_read()
1725 val = xive->tctxt_regs[TCTXT_EN1 >> 3]; in pnv_xive2_ic_tctxt_read()
1728 val = xive->tctxt_regs[reg]; in pnv_xive2_ic_tctxt_read()
1749 xive->tctxt_regs[reg] = val; in pnv_xive2_ic_tctxt_write()
1753 xive->tctxt_regs[TCTXT_EN0 >> 3] |= val; in pnv_xive2_ic_tctxt_write()
1756 xive->tctxt_regs[TCTXT_EN1 >> 3] |= val; in pnv_xive2_ic_tctxt_write()
1759 xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val; in pnv_xive2_ic_tctxt_write()
1762 xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val; in pnv_xive2_ic_tctxt_write()
1765 xive->tctxt_regs[reg] = val; in pnv_xive2_ic_tctxt_write()
1794 uint64_t val = -1; in pnv_xive2_xscom_read()
1861 * 0x000 - 0x7FF IPI interrupt (NPU)
1862 * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB)
1897 /* TODO: check IPI notify sub-page routing */ in pnv_xive2_ic_notify_write()
1918 return -1; in pnv_xive2_ic_notify_read()
1941 return -1; in pnv_xive2_ic_lsi_read()
1990 return -1; in pnv_xive2_ic_sync_read()
2006 hwaddr pg_offset_mask = (1ull << xive->ic_shift) - 1; in pnv_xive2_ic_sync_write()
2083 return xive->chip->chip_id << 8 | offset >> xive->ic_shift; in pnv_xive2_ic_tm_get_pir()
2095 return offset & ((1ull << xive->ic_shift) - 1); in pnv_xive2_ic_tm_get_hw_page_offset()
2100 PnvChip *chip = xive->chip; in pnv_xive2_get_indirect_tctx()
2113 return XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive2_get_indirect_tctx()
2124 uint64_t val = -1; in pnv_xive2_ic_tm_indirect_read()
2175 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive2_tm_write()
2185 XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); in pnv_xive2_tm_read()
2210 uint32_t page = addr >> xive->nvpg_shift; in pnv_xive2_nvc_read()
2217 return -1; in pnv_xive2_nvc_read()
2228 uint32_t page = addr >> xive->nvc_shift; in pnv_xive2_nvc_write()
2260 uint32_t page = addr >> xive->nvpg_shift; in pnv_xive2_nvpg_read()
2268 return -1; in pnv_xive2_nvpg_read()
2272 /* odd page - NVG */ in pnv_xive2_nvpg_read()
2275 /* even page - NVP */ in pnv_xive2_nvpg_read()
2285 uint32_t page = addr >> xive->nvpg_shift; in pnv_xive2_nvpg_write()
2297 /* odd page - NVG */ in pnv_xive2_nvpg_write()
2300 /* even page - NVP */ in pnv_xive2_nvpg_write()
2334 XiveSource *xsrc = &xive->ipi_source; in pnv_xive2_reset()
2335 Xive2EndSource *end_xsrc = &xive->end_source; in pnv_xive2_reset()
2337 xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities; in pnv_xive2_reset()
2338 xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config; in pnv_xive2_reset()
2341 xive->cq_regs[CQ_XIVE_CFG >> 3] |= in pnv_xive2_reset()
2342 SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id); in pnv_xive2_reset()
2345 xive->vc_regs[VC_ENDC_CFG >> 3] = in pnv_xive2_reset()
2347 xive->pc_regs[PC_NXC_PROC_CONFIG >> 3] = in pnv_xive2_reset()
2351 xive->ic_shift = xive->esb_shift = xive->end_shift = 16; in pnv_xive2_reset()
2352 xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16; in pnv_xive2_reset()
2355 if (memory_region_is_mapped(&xsrc->esb_mmio)) { in pnv_xive2_reset()
2356 memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio); in pnv_xive2_reset()
2359 if (memory_region_is_mapped(&end_xsrc->esb_mmio)) { in pnv_xive2_reset()
2360 memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio); in pnv_xive2_reset()
2365 * Maximum number of IRQs and ENDs supported by HW. Will be tuned by
2375 XiveSource *xsrc = &xive->ipi_source; in pnv_xive2_realize()
2376 Xive2EndSource *end_xsrc = &xive->end_source; in pnv_xive2_realize()
2380 pxc->parent_realize(dev, &local_err); in pnv_xive2_realize()
2386 assert(xive->chip); in pnv_xive2_realize()
2396 object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS, in pnv_xive2_realize()
2406 object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS, in pnv_xive2_realize()
2417 memory_region_init_io(&xive->xscom_regs, OBJECT(dev), in pnv_xive2_realize()
2418 &pnv_xive2_xscom_ops, xive, "xscom-xive", in pnv_xive2_realize()
2422 xive->ic_shift = 16; in pnv_xive2_realize()
2423 memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic", in pnv_xive2_realize()
2426 for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) { in pnv_xive2_realize()
2427 memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev), in pnv_xive2_realize()
2430 pnv_xive2_ic_regions[i].pgsize << xive->ic_shift); in pnv_xive2_realize()
2436 xive->esb_shift = 16; in pnv_xive2_realize()
2437 xive->end_shift = 16; in pnv_xive2_realize()
2438 memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb", in pnv_xive2_realize()
2440 memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end", in pnv_xive2_realize()
2444 xive->nvc_shift = 16; in pnv_xive2_realize()
2445 xive->nvpg_shift = 16; in pnv_xive2_realize()
2446 memory_region_init_io(&xive->nvc_mmio, OBJECT(dev), in pnv_xive2_realize()
2448 "xive-nvc", PNV10_XIVE2_NVC_SIZE); in pnv_xive2_realize()
2450 memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev), in pnv_xive2_realize()
2452 "xive-nvpg", PNV10_XIVE2_NVPG_SIZE); in pnv_xive2_realize()
2455 xive->tm_shift = 16; in pnv_xive2_realize()
2456 memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops, in pnv_xive2_realize()
2457 xive, "xive-tima", PNV10_XIVE2_TM_SIZE); in pnv_xive2_realize()
2463 DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0),
2464 DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0),
2465 DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0),
2466 DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0),
2467 DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0),
2468 DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0),
2480 object_initialize_child(obj, "ipi_source", &xive->ipi_source, in pnv_xive2_instance_init()
2482 object_initialize_child(obj, "end_source", &xive->end_source, in pnv_xive2_instance_init()
2489 const char compat_p10[] = "ibm,power10-xive-x"; in pnv_xive2_dt_xscom()
2517 xdc->dt_xscom = pnv_xive2_dt_xscom; in pnv_xive2_class_init()
2519 dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)"; in pnv_xive2_class_init()
2521 &pxc->parent_realize); in pnv_xive2_class_init()
2524 xrc->get_eas = pnv_xive2_get_eas; in pnv_xive2_class_init()
2525 xrc->get_pq = pnv_xive2_get_pq; in pnv_xive2_class_init()
2526 xrc->set_pq = pnv_xive2_set_pq; in pnv_xive2_class_init()
2527 xrc->get_end = pnv_xive2_get_end; in pnv_xive2_class_init()
2528 xrc->write_end = pnv_xive2_write_end; in pnv_xive2_class_init()
2529 xrc->get_nvp = pnv_xive2_get_nvp; in pnv_xive2_class_init()
2530 xrc->write_nvp = pnv_xive2_write_nvp; in pnv_xive2_class_init()
2531 xrc->get_nvgc = pnv_xive2_get_nvgc; in pnv_xive2_class_init()
2532 xrc->write_nvgc = pnv_xive2_write_nvgc; in pnv_xive2_class_init()
2533 xrc->get_config = pnv_xive2_get_config; in pnv_xive2_class_init()
2534 xrc->get_block_id = pnv_xive2_get_block_id; in pnv_xive2_class_init()
2536 xnc->notify = pnv_xive2_notify; in pnv_xive2_class_init()
2538 xpc->match_nvt = pnv_xive2_match_nvt; in pnv_xive2_class_init()
2539 xpc->get_config = pnv_xive2_presenter_get_config; in pnv_xive2_class_init()
2540 xpc->broadcast = pnv_xive2_broadcast; in pnv_xive2_class_init()
2570 uint64_t vsd = xive->vsds[VST_ESB][blk]; in type_init()
2582 uint64_t vsd = xive->vsds[type][blk]; in pnv_xive2_vst_per_subpage()
2598 xive2_error(xive, "VST: invalid %s entry!?", info->name); in pnv_xive2_vst_per_subpage()
2606 xive2_error(xive, "VST: invalid %s page shift %d", info->name, in pnv_xive2_vst_per_subpage()
2611 return (1ull << page_shift) / info->size; in pnv_xive2_vst_per_subpage()
2618 uint8_t chip_id = xive->chip->chip_id; in pnv_xive2_pic_print_info()
2629 blk, srcno0, srcno0 + nr_esbs - 1); in pnv_xive2_pic_print_info()
2630 xive_source_pic_print_info(&xive->ipi_source, srcno0, buf); in pnv_xive2_pic_print_info()
2633 blk, srcno0, srcno0 + nr_esbs - 1); in pnv_xive2_pic_print_info()
2657 chip_id, blk, 0, XIVE2_NVP_COUNT - 1); in pnv_xive2_pic_print_info()
2666 chip_id, blk, 0, XIVE2_NVP_COUNT - 1); in pnv_xive2_pic_print_info()
2675 chip_id, blk, 0, XIVE2_NVP_COUNT - 1); in pnv_xive2_pic_print_info()