Lines Matching +full:intc +full:- +full:no +full:- +full:eoi
4 * Copyright (c) 2004-2005 Fabrice Bellard
28 #include "hw/intc/i8259.h"
29 #include "hw/intc/ioapic.h"
30 #include "hw/intc/ioapic_internal.h"
32 #include "hw/qdev-properties.h"
35 #include "hw/i386/apic-msidef.h"
36 #include "hw/i386/x86-iommu.h"
65 info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1; in ioapic_entry_parse()
66 info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1; in ioapic_entry_parse()
73 info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff; in ioapic_entry_parse()
74 info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1; in ioapic_entry_parse()
75 info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \ in ioapic_entry_parse()
77 if (info->delivery_mode == IOAPIC_DM_EXTINT) { in ioapic_entry_parse()
78 info->vector = pic_read_irq(isa_pic); in ioapic_entry_parse()
80 info->vector = entry & IOAPIC_VECTOR_MASK; in ioapic_entry_parse()
83 info->addr = APIC_DEFAULT_ADDRESS | \ in ioapic_entry_parse()
84 (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \ in ioapic_entry_parse()
85 (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT); in ioapic_entry_parse()
86 info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \ in ioapic_entry_parse()
87 (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \ in ioapic_entry_parse()
88 (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT); in ioapic_entry_parse()
93 AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as; in ioapic_service()
101 if (s->irr & mask) { in ioapic_service()
104 entry = s->ioredtbl[i]; in ioapic_service()
108 s->irr &= ~mask; in ioapic_service()
110 coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR; in ioapic_service()
112 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR; in ioapic_service()
134 /* No matter whether IR is enabled, we translate in ioapic_service()
157 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps in ioapic_set_irq()
158 * to GSI 2. GSI maps to ioapic 1-1. This is not in ioapic_set_irq()
168 uint64_t entry = s->ioredtbl[vector]; in ioapic_set_irq()
174 s->irr |= mask; in ioapic_set_irq()
179 s->irr &= ~mask; in ioapic_set_irq()
185 s->irr |= mask; in ioapic_set_irq()
201 ioapic_entry_parse(s->ioredtbl[i], &info); in ioapic_update_kvm_routes()
237 entry = s->ioredtbl[n]; in ioapic_eoi_broadcast()
251 * remote-irr of the table entry should be bypassed too in ioapic_eoi_broadcast()
253 * they're bound to the IRQ, to make sure to EOI the in ioapic_eoi_broadcast()
256 * Note: We still need to go through the irr & remote-irr in ioapic_eoi_broadcast()
268 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR; in ioapic_eoi_broadcast()
270 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) { in ioapic_eoi_broadcast()
271 ++s->irq_eoi[n]; in ioapic_eoi_broadcast()
272 if (s->irq_eoi[n] >= SUCCESSIVE_IRQ_MAX_COUNT) { in ioapic_eoi_broadcast()
275 * during eoi broadcast, and this lets a buggy guest make in ioapic_eoi_broadcast()
277 * level-triggered interrupt. Emulate this behavior if we in ioapic_eoi_broadcast()
280 s->irq_eoi[n] = 0; in ioapic_eoi_broadcast()
281 timer_mod_anticipate(s->delayed_ioapic_service_timer, in ioapic_eoi_broadcast()
289 s->irq_eoi[n] = 0; in ioapic_eoi_broadcast()
306 val = s->ioregsel; in ioapic_mem_read()
312 switch (s->ioregsel) { in ioapic_mem_read()
315 val = s->id << IOAPIC_ID_SHIFT; in ioapic_mem_read()
318 val = s->version | in ioapic_mem_read()
319 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT); in ioapic_mem_read()
322 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; in ioapic_mem_read()
324 if (s->ioregsel & 1) { in ioapic_mem_read()
325 val = s->ioredtbl[index] >> 32; in ioapic_mem_read()
327 val = s->ioredtbl[index] & 0xffffffff; in ioapic_mem_read()
334 trace_ioapic_mem_read(addr, s->ioregsel, size, val); in ioapic_mem_read()
344 * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
345 * Otherwise, we simulate the EOI message manually by changing the trigger
352 * cleared by IOAPIC hardware when configured as edge-triggered
355 * Without this, level-triggered interrupts in IR mode might fail to
362 /* Edge-triggered interrupts, make sure remote IRR is zero */ in ioapic_fix_edge_remote_irr()
375 trace_ioapic_mem_write(addr, s->ioregsel, size, val); in ioapic_mem_write()
379 s->ioregsel = val; in ioapic_mem_write()
385 switch (s->ioregsel) { in ioapic_mem_write()
387 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK; in ioapic_mem_write()
393 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1; in ioapic_mem_write()
395 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS; in ioapic_mem_write()
396 if (s->ioregsel & 1) { in ioapic_mem_write()
397 s->ioredtbl[index] &= 0xffffffff; in ioapic_mem_write()
398 s->ioredtbl[index] |= (uint64_t)val << 32; in ioapic_mem_write()
400 s->ioredtbl[index] &= ~0xffffffffULL; in ioapic_mem_write()
401 s->ioredtbl[index] |= val; in ioapic_mem_write()
404 s->ioredtbl[index] &= IOAPIC_RW_BITS; in ioapic_mem_write()
405 s->ioredtbl[index] |= ro_bits; in ioapic_mem_write()
406 s->irq_eoi[index] = 0; in ioapic_mem_write()
407 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]); in ioapic_mem_write()
414 /* Explicit EOI is only supported for IOAPIC version 0x20 */ in ioapic_mem_write()
415 if (size != 4 || s->version != 0x20) { in ioapic_mem_write()
453 if (s->version != 0x11 && s->version != 0x20) { in ioapic_realize()
459 memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s, in ioapic_realize()
462 s->delayed_ioapic_service_timer = in ioapic_realize()
468 s->machine_done.notify = ioapic_machine_done_notify; in ioapic_realize()
469 qemu_add_machine_init_done_notifier(&s->machine_done); in ioapic_realize()
476 timer_free(s->delayed_ioapic_service_timer); in ioapic_unrealize()
488 k->realize = ioapic_realize; in ioapic_class_init()
489 k->unrealize = ioapic_unrealize; in ioapic_class_init()
494 k->post_load = ioapic_update_kvm_routes; in ioapic_class_init()