hw/i386/intel_iommu_internal.h

2  * QEMU emulation of an Intel IOMMU (VT-d)
21  * Lots of defines copied from kernel/include/linux/intel-iommu.h:
22  *   Copyright (C) 2006-2008 Intel Corporation
37 #define DMAR_CAP_REG_HI         0xc  /* High 32-bit of DMAR_CAP_REG */
56 #define DMAR_PHMBASE_REG        0x70 /* PMRR high base addr */
58 #define DMAR_PHMLIMIT_REG       0x78 /* PMRR high limit */
113 #define VTD_INTERRUPT_ADDR_SIZE     (VTD_INTERRUPT_ADDR_LAST - \
124 #define VTD_TLB_DSI_FLUSH           (2ULL << 60) /* Domain-selective */
125 #define VTD_TLB_PSI_FLUSH           (3ULL << 60) /* Page-selective */
203 #define VTD_CAP_NFR                 ((DMAR_FRCD_REG_NR - 1) << 40)
204 #define VTD_DOMAIN_ID_SHIFT         16  /* 16-bit domain id for 64K domains */
205 #define VTD_DOMAIN_ID_MASK          ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
206 #define VTD_CAP_ND                  (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
208 #define VTD_CAP_MGAW(aw)            ((((aw) - 1) & 0x3fULL) << 16)
219 #define VTD_PASID_ID_MASK           ((1ULL << VTD_PASID_ID_SHIFT) - 1)
224  /* 39-bit AGAW, 3-level page-table */
226  /* 48-bit AGAW, 4-level page-table */
263 /* For the high 64-bit of 128-bit */
271 /* For the low 64-bit of 128-bit */
278     VTD_FR_ROOT_ENTRY_P = 1,    /* The Present(P) field of root-entry is 0 */
279     VTD_FR_CONTEXT_ENTRY_P,     /* The Present(P) field of context-entry is 0 */
280     VTD_FR_CONTEXT_ENTRY_INV,   /* Invalid programming of a context-entry */
281     VTD_FR_ADDR_BEYOND_MGAW,    /* Input-address above (2^x-1) */
284     /* Fail to access a second-level paging entry (not SL_PML4E) */
286     VTD_FR_ROOT_TABLE_INV,      /* Fail to access a root-entry */
287     VTD_FR_CONTEXT_TABLE_INV,   /* Fail to access a context-entry */
288     /* Non-zero reserved field in a present root-entry */
290     /* Non-zero reserved field in a present context-entry */
292     /* Non-zero reserved field in a second-level paging entry with at lease one
298      * context-entry.
310     VTD_FR_IR_IRTE_RSVD = 0x24,  /* IRTE Rsvd field non-zero with
314     VTD_FR_IR_SID_ERR = 0x26,   /* Invalid Source-ID */
325     /* Fail to access a first-level paging entry (not FS_PML4E) */
328     /* Non-zero reserved field in present first-stage paging entry */
343 /* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
379 #define VTD_INV_DESC_ALL_ONE            -1ULL
382 #define VTD_INV_DESC_CC                 0x1 /* Context-cache Invalidate Desc */
388 #define VTD_INV_DESC_PIOTLB             0x6 /* PASID-IOTLB Invalidate Desc */
389 #define VTD_INV_DESC_PC                 0x7 /* PASID-cache Invalidate Desc */
390 #define VTD_INV_DESC_DEV_PIOTLB         0x8 /* PASID-based-DIOTLB inv_desc*/
401 /* Masks for Context-cache Invalidation Descriptor */
493 /* Information about page-selective IOTLB invalidate */
507 #define VTD_PAGE_MASK_4K            (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
509 #define VTD_PAGE_MASK_2M            (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
511 #define VTD_PAGE_MASK_1G            (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
540 #define VTD_CONTEXT_ENTRY_AW        7ULL /* Adjusted guest-address-width */
573 #define VTD_SM_PASID_ENTRY_AW          7ULL /* Adjusted guest-address-width */
605 #define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))