Lines Matching +full:dte +full:- +full:mode
2 * QEMU emulation of AMD IOMMU (AMD-Vi)
4 * Copyright (C) 2011 Eduard - Gabriel Munteanu
30 #include "qemu/error-report.h"
33 #include "hw/i386/apic-msidef.h"
34 #include "hw/qdev-properties.h"
37 /* used AMD-Vi MMIO registers */
63 AMDVIState *iommu_state; /* AMDVI - one per machine */
83 if (s->xtsup) { in amdvi_extended_feature_register()
94 stq_le_p(&s->mmior[addr], val); in amdvi_set_quad()
95 stq_le_p(&s->romask[addr], romask); in amdvi_set_quad()
96 stq_le_p(&s->w1cmask[addr], w1cmask); in amdvi_set_quad()
101 return lduw_le_p(&s->mmior[addr]); in amdvi_readw()
106 return ldl_le_p(&s->mmior[addr]); in amdvi_readl()
111 return ldq_le_p(&s->mmior[addr]); in amdvi_readq()
117 stq_le_p(&s->mmior[addr], val); in amdvi_writeq_raw()
123 uint16_t romask = lduw_le_p(&s->romask[addr]); in amdvi_writew()
124 uint16_t w1cmask = lduw_le_p(&s->w1cmask[addr]); in amdvi_writew()
125 uint16_t oldval = lduw_le_p(&s->mmior[addr]); in amdvi_writew()
126 stw_le_p(&s->mmior[addr], in amdvi_writew()
132 uint32_t romask = ldl_le_p(&s->romask[addr]); in amdvi_writel()
133 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]); in amdvi_writel()
134 uint32_t oldval = ldl_le_p(&s->mmior[addr]); in amdvi_writel()
135 stl_le_p(&s->mmior[addr], in amdvi_writel()
141 uint64_t romask = ldq_le_p(&s->romask[addr]); in amdvi_writeq()
142 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]); in amdvi_writeq()
143 uint32_t oldval = ldq_le_p(&s->mmior[addr]); in amdvi_writeq()
144 stq_le_p(&s->mmior[addr], in amdvi_writeq()
148 /* OR a 64-bit register with a 64-bit value */
154 /* OR a 64-bit register with a 64-bit value storing result in the register */
160 /* AND a 64-bit register with a 64-bit value storing result in the register */
170 .requester_id = pci_requester_id(&s->pci.dev) in amdvi_generate_msi_interrupt()
173 if (msi_enabled(&s->pci.dev)) { in amdvi_generate_msi_interrupt()
174 msg = msi_get_message(&s->pci.dev, 0); in amdvi_generate_msi_interrupt()
183 if (!s->evtlog_enabled || amdvi_test_mask(s, AMDVI_MMIO_STATUS, in amdvi_log_event()
189 if (s->evtlog_tail >= s->evtlog_len) { in amdvi_log_event()
196 if (dma_memory_write(&address_space_memory, s->evtlog + s->evtlog_tail, in amdvi_log_event()
198 trace_amdvi_evntlog_fail(s->evtlog, s->evtlog_tail); in amdvi_log_event()
201 s->evtlog_tail += AMDVI_EVENT_LEN; in amdvi_log_event()
216 * 0:15 -> DeviceID
217 * 48:63 -> event type + miscellaneous info
218 * 64:127 -> related address
242 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_page_fault()
259 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_devtab_error()
272 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_command_error()
313 pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, in amdvi_log_pagetab_error()
332 return g_hash_table_lookup(s->iotlb, &key); in amdvi_iotlb_lookup()
337 assert(s->iotlb); in amdvi_iotlb_reset()
339 g_hash_table_remove_all(s->iotlb); in amdvi_iotlb_reset()
347 return entry->devid == devid; in amdvi_iotlb_remove_by_devid()
355 g_hash_table_remove(s->iotlb, &key); in amdvi_iotlb_remove_page()
371 if (g_hash_table_size(s->iotlb) >= AMDVI_IOTLB_MAX_SIZE) { in amdvi_update_iotlb()
375 entry->domid = domid; in amdvi_update_iotlb()
376 entry->perms = to_cache.perm; in amdvi_update_iotlb()
377 entry->translated_addr = to_cache.translated_addr; in amdvi_update_iotlb()
378 entry->page_mask = to_cache.addr_mask; in amdvi_update_iotlb()
380 g_hash_table_replace(s->iotlb, key, entry); in amdvi_update_iotlb()
392 s->cmdbuf + s->cmdbuf_head); in amdvi_completion_wait()
418 s->cmdbuf + s->cmdbuf_head); in amdvi_inval_devtab_entry()
430 s->cmdbuf + s->cmdbuf_head); in amdvi_complete_ppr()
445 s->cmdbuf + s->cmdbuf_head); in amdvi_inval_all()
460 return entry->domid == domid; in amdvi_iotlb_remove_by_domid()
463 /* we don't have devid - we can't remove pages by address */
471 s->cmdbuf + s->cmdbuf_head); in amdvi_inval_pages()
474 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_domid, in amdvi_inval_pages()
485 s->cmdbuf + s->cmdbuf_head); in amdvi_prefetch_pages()
495 s->cmdbuf + s->cmdbuf_head); in amdvi_inval_inttable()
515 s->cmdbuf + s->cmdbuf_head); in iommu_inval_iotlb()
520 g_hash_table_foreach_remove(s->iotlb, amdvi_iotlb_remove_by_devid, in iommu_inval_iotlb()
534 if (dma_memory_read(&address_space_memory, s->cmdbuf + s->cmdbuf_head, in amdvi_cmdbuf_exec()
536 trace_amdvi_command_read_fail(s->cmdbuf, s->cmdbuf_head); in amdvi_cmdbuf_exec()
537 amdvi_log_command_error(s, s->cmdbuf + s->cmdbuf_head); in amdvi_cmdbuf_exec()
570 s->cmdbuf + s->cmdbuf_head); in amdvi_cmdbuf_exec()
576 if (!s->cmdbuf_enabled) { in amdvi_cmdbuf_run()
582 while (s->cmdbuf_head != s->cmdbuf_tail) { in amdvi_cmdbuf_run()
583 trace_amdvi_command_exec(s->cmdbuf_head, s->cmdbuf_tail, s->cmdbuf); in amdvi_cmdbuf_run()
585 s->cmdbuf_head += AMDVI_COMMAND_SIZE; in amdvi_cmdbuf_run()
586 amdvi_writeq_raw(s, AMDVI_MMIO_COMMAND_HEAD, s->cmdbuf_head); in amdvi_cmdbuf_run()
589 if (s->cmdbuf_head >= s->cmdbuf_len * AMDVI_COMMAND_SIZE) { in amdvi_cmdbuf_run()
590 s->cmdbuf_head = 0; in amdvi_cmdbuf_run()
613 uint64_t val = -1; in amdvi_mmio_read()
616 return (uint64_t)-1; in amdvi_mmio_read()
634 s->enabled = !!(control & AMDVI_MMIO_CONTROL_AMDVIEN); in amdvi_handle_control_write()
636 s->ats_enabled = !!(control & AMDVI_MMIO_CONTROL_HTTUNEN); in amdvi_handle_control_write()
637 s->evtlog_enabled = s->enabled && !!(control & in amdvi_handle_control_write()
640 s->evtlog_intr = !!(control & AMDVI_MMIO_CONTROL_EVENTINTEN); in amdvi_handle_control_write()
641 s->completion_wait_intr = !!(control & AMDVI_MMIO_CONTROL_COMWAITINTEN); in amdvi_handle_control_write()
642 s->cmdbuf_enabled = s->enabled && !!(control & in amdvi_handle_control_write()
644 s->ga_enabled = !!(control & AMDVI_MMIO_CONTROL_GAEN); in amdvi_handle_control_write()
647 if (s->cmdbuf_enabled) { in amdvi_handle_control_write()
652 if (s->evtlog_enabled) { in amdvi_handle_control_write()
666 s->devtab = (val & AMDVI_MMIO_DEVTAB_BASE_MASK); in amdvi_handle_devtab_write()
669 s->devtab_len = ((val & AMDVI_MMIO_DEVTAB_SIZE_MASK) + 1 * in amdvi_handle_devtab_write()
676 s->cmdbuf_head = amdvi_readq(s, AMDVI_MMIO_COMMAND_HEAD) in amdvi_handle_cmdhead_write()
683 s->cmdbuf = amdvi_readq(s, AMDVI_MMIO_COMMAND_BASE) in amdvi_handle_cmdbase_write()
685 s->cmdbuf_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_CMDBUF_SIZE_BYTE) in amdvi_handle_cmdbase_write()
687 s->cmdbuf_head = s->cmdbuf_tail = 0; in amdvi_handle_cmdbase_write()
692 s->cmdbuf_tail = amdvi_readq(s, AMDVI_MMIO_COMMAND_TAIL) in amdvi_handle_cmdtail_write()
700 s->excl_limit = (val & AMDVI_MMIO_EXCL_LIMIT_MASK) | in amdvi_handle_excllim_write()
707 s->evtlog = val & AMDVI_MMIO_EVTLOG_BASE_MASK; in amdvi_handle_evtbase_write()
708 s->evtlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_EVTLOG_SIZE_BYTE) in amdvi_handle_evtbase_write()
715 s->evtlog_tail = val & AMDVI_MMIO_EVTLOG_TAIL_MASK; in amdvi_handle_evttail_write()
721 s->evtlog_head = val & AMDVI_MMIO_EVTLOG_HEAD_MASK; in amdvi_handle_evthead_write()
727 s->ppr_log = val & AMDVI_MMIO_PPRLOG_BASE_MASK; in amdvi_handle_pprbase_write()
728 s->pprlog_len = 1UL << (amdvi_readq(s, AMDVI_MMIO_PPRLOG_SIZE_BYTE) in amdvi_handle_pprbase_write()
735 s->pprlog_head = val & AMDVI_MMIO_PPRLOG_HEAD_MASK; in amdvi_handle_pprhead_write()
741 s->pprlog_tail = val & AMDVI_MMIO_PPRLOG_TAIL_MASK; in amdvi_handle_pprtail_write()
795 /* FIXME - make sure System Software has finished writing in case in amdvi_mmio_write()
823 /* PPR log base - unused for now */ in amdvi_mmio_write()
828 /* PPR log head - also unused for now */ in amdvi_mmio_write()
833 /* PPR log tail - unused for now */ in amdvi_mmio_write()
849 uint64_t *dte) in amdvi_validate_dte() argument
851 if ((dte[0] & AMDVI_DTE_LOWER_QUAD_RESERVED) in amdvi_validate_dte()
852 || (dte[1] & AMDVI_DTE_MIDDLE_QUAD_RESERVED) in amdvi_validate_dte()
853 || (dte[2] & AMDVI_DTE_UPPER_QUAD_RESERVED) || dte[3]) { in amdvi_validate_dte()
855 s->devtab + in amdvi_validate_dte()
868 if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, in amdvi_get_dte()
870 trace_amdvi_dte_get_fail(s->devtab, offset); in amdvi_get_dte()
871 /* log error accessing dte */ in amdvi_get_dte()
872 amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); in amdvi_get_dte()
885 /* get pte translation mode */
901 return ~((1ULL << page_mask) - 1); in pte_override_page_mask()
906 return ~((1UL << ((oldlevel * 9) + 3)) - 1); in pte_get_page_mask()
926 static void amdvi_page_walk(AMDVIAddressSpace *as, uint64_t *dte, in amdvi_page_walk() argument
931 uint64_t pte = dte[0], pte_addr, page_mask; in amdvi_page_walk()
933 /* make sure the DTE has TV = 1 */ in amdvi_page_walk()
949 amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); in amdvi_page_walk()
958 pte = amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); in amdvi_page_walk()
973 ret->iova = addr & page_mask; in amdvi_page_walk()
974 ret->translated_addr = (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; in amdvi_page_walk()
975 ret->addr_mask = ~page_mask; in amdvi_page_walk()
976 ret->perm = amdvi_get_perms(pte); in amdvi_page_walk()
980 ret->iova = addr & AMDVI_PAGE_MASK_4K; in amdvi_page_walk()
981 ret->translated_addr = addr & AMDVI_PAGE_MASK_4K; in amdvi_page_walk()
982 ret->addr_mask = ~AMDVI_PAGE_MASK_4K; in amdvi_page_walk()
983 ret->perm = amdvi_get_perms(pte); in amdvi_page_walk()
989 AMDVIState *s = as->iommu_state; in amdvi_do_translate()
990 uint16_t devid = PCI_BUILD_BDF(as->bus_num, as->devfn); in amdvi_do_translate()
996 PCI_FUNC(devid), addr, iotlb_entry->translated_addr); in amdvi_do_translate()
997 ret->iova = addr & ~iotlb_entry->page_mask; in amdvi_do_translate()
998 ret->translated_addr = iotlb_entry->translated_addr; in amdvi_do_translate()
999 ret->addr_mask = iotlb_entry->page_mask; in amdvi_do_translate()
1000 ret->perm = iotlb_entry->perms; in amdvi_do_translate()
1021 ret->iova = addr & AMDVI_PAGE_MASK_4K; in amdvi_do_translate()
1022 ret->translated_addr = addr & AMDVI_PAGE_MASK_4K; in amdvi_do_translate()
1023 ret->addr_mask = ~AMDVI_PAGE_MASK_4K; in amdvi_do_translate()
1024 ret->perm = IOMMU_RW; in amdvi_do_translate()
1036 AMDVIState *s = as->iommu_state; in amdvi_translate()
1045 if (!s->enabled) { in amdvi_translate()
1046 /* AMDVI disabled - corresponds to iommu=off not in amdvi_translate()
1063 trace_amdvi_translation_result(as->bus_num, PCI_SLOT(as->devfn), in amdvi_translate()
1064 PCI_FUNC(as->devfn), addr, ret.translated_addr); in amdvi_translate()
1068 static int amdvi_get_irte(AMDVIState *s, MSIMessage *origin, uint64_t *dte, in amdvi_get_irte() argument
1073 irte_root = dte[2] & AMDVI_IR_PHYS_ADDR_MASK; in amdvi_get_irte()
1074 offset = (origin->data & AMDVI_IRTE_OFFSET) << 2; in amdvi_get_irte()
1081 return -AMDVI_IR_GET_IRTE; in amdvi_get_irte()
1084 trace_amdvi_ir_irte_val(irte->val); in amdvi_get_irte()
1092 uint64_t *dte, in amdvi_int_remap_legacy() argument
1100 ret = amdvi_get_irte(iommu, origin, dte, &irte, sid); in amdvi_int_remap_legacy()
1107 return -AMDVI_IR_TARGET_ABORT; in amdvi_int_remap_legacy()
1111 error_report_once("guest mode is not zero"); in amdvi_int_remap_legacy()
1112 return -AMDVI_IR_ERR; in amdvi_int_remap_legacy()
1117 return -AMDVI_IR_ERR; in amdvi_int_remap_legacy()
1120 irq->delivery_mode = irte.fields.int_type; in amdvi_int_remap_legacy()
1121 irq->vector = irte.fields.vector; in amdvi_int_remap_legacy()
1122 irq->dest_mode = irte.fields.dm; in amdvi_int_remap_legacy()
1123 irq->redir_hint = irte.fields.rq_eoi; in amdvi_int_remap_legacy()
1124 irq->dest = irte.fields.destination; in amdvi_int_remap_legacy()
1129 static int amdvi_get_irte_ga(AMDVIState *s, MSIMessage *origin, uint64_t *dte, in amdvi_get_irte_ga() argument
1134 irte_root = dte[2] & AMDVI_IR_PHYS_ADDR_MASK; in amdvi_get_irte_ga()
1135 offset = (origin->data & AMDVI_IRTE_OFFSET) << 4; in amdvi_get_irte_ga()
1141 return -AMDVI_IR_GET_IRTE; in amdvi_get_irte_ga()
1144 trace_amdvi_ir_irte_ga_val(irte->hi.val, irte->lo.val); in amdvi_get_irte_ga()
1151 uint64_t *dte, in amdvi_int_remap_ga() argument
1159 ret = amdvi_get_irte_ga(iommu, origin, dte, &irte, sid); in amdvi_int_remap_ga()
1166 return -AMDVI_IR_TARGET_ABORT; in amdvi_int_remap_ga()
1170 error_report_once("guest mode is not zero"); in amdvi_int_remap_ga()
1171 return -AMDVI_IR_ERR; in amdvi_int_remap_ga()
1176 return -AMDVI_IR_ERR; in amdvi_int_remap_ga()
1179 irq->delivery_mode = irte.lo.fields_remap.int_type; in amdvi_int_remap_ga()
1180 irq->vector = irte.hi.fields.vector; in amdvi_int_remap_ga()
1181 irq->dest_mode = irte.lo.fields_remap.dm; in amdvi_int_remap_ga()
1182 irq->redir_hint = irte.lo.fields_remap.rq_eoi; in amdvi_int_remap_ga()
1183 if (iommu->xtsup) { in amdvi_int_remap_ga()
1184 irq->dest = irte.lo.fields_remap.destination | in amdvi_int_remap_ga()
1187 irq->dest = irte.lo.fields_remap.destination & 0xff; in amdvi_int_remap_ga()
1196 uint64_t *dte, in __amdvi_int_remap_msi() argument
1203 int_ctl = (dte[2] >> AMDVI_IR_INTCTL_SHIFT) & 3; in __amdvi_int_remap_msi()
1214 return -AMDVI_IR_TARGET_ABORT; in __amdvi_int_remap_msi()
1217 return -AMDVI_IR_ERR; in __amdvi_int_remap_msi()
1220 if (iommu->ga_enabled) { in __amdvi_int_remap_msi()
1221 ret = amdvi_int_remap_ga(iommu, origin, translated, dte, irq, sid); in __amdvi_int_remap_msi()
1223 ret = amdvi_int_remap_legacy(iommu, origin, translated, dte, irq, sid); in __amdvi_int_remap_msi()
1229 /* Interrupt remapping for MSI/MSI-X entry */
1237 uint64_t dte[4] = { 0 }; in amdvi_int_remap_msi() local
1245 * IO-APIC or PCI device. If interrupt is from PCI device then it will in amdvi_int_remap_msi()
1246 * have a valid requester id but if the interrupt is from IO-APIC in amdvi_int_remap_msi()
1253 trace_amdvi_ir_remap_msi_req(origin->address, origin->data, sid); in amdvi_int_remap_msi()
1256 if (!iommu || !iommu->devtab_len) { in amdvi_int_remap_msi()
1261 if (!amdvi_get_dte(iommu, sid, dte)) { in amdvi_int_remap_msi()
1262 return -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1265 /* Check if IR is enabled in DTE */ in amdvi_int_remap_msi()
1266 if (!(dte[2] & AMDVI_IR_REMAP_ENABLE)) { in amdvi_int_remap_msi()
1275 "remapping in amd-iommu."); in amdvi_int_remap_msi()
1276 return -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1279 if (origin->address < AMDVI_INT_ADDR_FIRST || in amdvi_int_remap_msi()
1280 origin->address + sizeof(origin->data) > AMDVI_INT_ADDR_LAST + 1) { in amdvi_int_remap_msi()
1282 return -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1288 * See MSI/MSI-X format: in amdvi_int_remap_msi()
1292 delivery_mode = (origin->data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 7; in amdvi_int_remap_msi()
1298 ret = __amdvi_int_remap_msi(iommu, origin, translated, dte, &irq, sid); in amdvi_int_remap_msi()
1309 ret = -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1312 pass = dte[2] & AMDVI_DEV_NMI_PASS_MASK; in amdvi_int_remap_msi()
1316 pass = dte[2] & AMDVI_DEV_INT_PASS_MASK; in amdvi_int_remap_msi()
1320 pass = dte[2] & AMDVI_DEV_EINT_PASS_MASK; in amdvi_int_remap_msi()
1325 ret = -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1335 * mode. The dest_mode 1 is valid for fixed and arbitrated interrupts in amdvi_int_remap_msi()
1338 dest_mode = (origin->address >> MSI_ADDR_DEST_MODE_SHIFT) & 1; in amdvi_int_remap_msi()
1341 ret = -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1349 ret = -AMDVI_IR_ERR; in amdvi_int_remap_msi()
1354 trace_amdvi_ir_remap_msi(origin->address, origin->data, in amdvi_int_remap_msi()
1355 translated->address, translated->data); in amdvi_int_remap_msi()
1396 apic_get_class(NULL)->send_msi(&to); in amdvi_mem_ir_write()
1431 iommu_as = s->address_spaces[bus_num]; in amdvi_host_dma_iommu()
1436 s->address_spaces[bus_num] = iommu_as; in amdvi_host_dma_iommu()
1439 /* set up AMD-Vi region */ in amdvi_host_dma_iommu()
1444 iommu_as[devfn]->bus_num = (uint8_t)bus_num; in amdvi_host_dma_iommu()
1445 iommu_as[devfn]->devfn = (uint8_t)devfn; in amdvi_host_dma_iommu()
1446 iommu_as[devfn]->iommu_state = s; in amdvi_host_dma_iommu()
1454 * |--------------------+-------------------+----------| in amdvi_host_dma_iommu()
1456 * |--------------------+-------------------+----------+ in amdvi_host_dma_iommu()
1457 * | amdvi-root | 00000000-ffffffff | 0 | in amdvi_host_dma_iommu()
1458 * | amdvi-iommu_nodma | 00000000-ffffffff | 0 | in amdvi_host_dma_iommu()
1459 * | amdvi-iommu_ir | fee00000-feefffff | 1 | in amdvi_host_dma_iommu()
1460 * |--------------------+-------------------+----------| in amdvi_host_dma_iommu()
1462 memory_region_init_iommu(&amdvi_dev_as->iommu, in amdvi_host_dma_iommu()
1463 sizeof(amdvi_dev_as->iommu), in amdvi_host_dma_iommu()
1467 memory_region_init(&amdvi_dev_as->root, OBJECT(s), in amdvi_host_dma_iommu()
1469 address_space_init(&amdvi_dev_as->as, &amdvi_dev_as->root, name); in amdvi_host_dma_iommu()
1470 memory_region_add_subregion_overlap(&amdvi_dev_as->root, 0, in amdvi_host_dma_iommu()
1471 MEMORY_REGION(&amdvi_dev_as->iommu), in amdvi_host_dma_iommu()
1475 memory_region_init_alias(&amdvi_dev_as->iommu_nodma, OBJECT(s), in amdvi_host_dma_iommu()
1476 "amdvi-sys", &s->mr_sys, 0, in amdvi_host_dma_iommu()
1477 memory_region_size(&s->mr_sys)); in amdvi_host_dma_iommu()
1478 memory_region_add_subregion_overlap(&amdvi_dev_as->root, 0, in amdvi_host_dma_iommu()
1479 &amdvi_dev_as->iommu_nodma, in amdvi_host_dma_iommu()
1482 memory_region_init_alias(&amdvi_dev_as->iommu_ir, OBJECT(s), in amdvi_host_dma_iommu()
1483 "amdvi-ir", &s->mr_ir, 0, in amdvi_host_dma_iommu()
1484 memory_region_size(&s->mr_ir)); in amdvi_host_dma_iommu()
1485 memory_region_add_subregion_overlap(MEMORY_REGION(&amdvi_dev_as->iommu), in amdvi_host_dma_iommu()
1487 &amdvi_dev_as->iommu_ir, 1); in amdvi_host_dma_iommu()
1489 if (!x86_iommu->pt_supported) { in amdvi_host_dma_iommu()
1490 memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, false); in amdvi_host_dma_iommu()
1491 memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), in amdvi_host_dma_iommu()
1494 memory_region_set_enabled(MEMORY_REGION(&amdvi_dev_as->iommu), in amdvi_host_dma_iommu()
1496 memory_region_set_enabled(&amdvi_dev_as->iommu_nodma, true); in amdvi_host_dma_iommu()
1499 return &iommu_as[devfn]->as; in amdvi_host_dma_iommu()
1531 "currently supported", as->bus_num, PCI_SLOT(as->devfn), in amdvi_iommu_notify_flag_changed()
1532 PCI_FUNC(as->devfn)); in amdvi_iommu_notify_flag_changed()
1533 return -EINVAL; in amdvi_iommu_notify_flag_changed()
1542 s->devtab_len = 0; in amdvi_init()
1543 s->cmdbuf_len = 0; in amdvi_init()
1544 s->cmdbuf_head = 0; in amdvi_init()
1545 s->cmdbuf_tail = 0; in amdvi_init()
1546 s->evtlog_head = 0; in amdvi_init()
1547 s->evtlog_tail = 0; in amdvi_init()
1548 s->excl_enabled = false; in amdvi_init()
1549 s->excl_allow = false; in amdvi_init()
1550 s->mmio_enabled = false; in amdvi_init()
1551 s->enabled = false; in amdvi_init()
1552 s->ats_enabled = false; in amdvi_init()
1553 s->cmdbuf_enabled = false; in amdvi_init()
1556 memset(s->mmior, 0, AMDVI_MMIO_SIZE); in amdvi_init()
1573 s->capab_offset = ret; in amdvi_pci_realize()
1591 pci_config_set_prog_interface(pdev->config, 0); in amdvi_pci_realize()
1594 pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES); in amdvi_pci_realize()
1595 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, in amdvi_pci_realize()
1597 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, in amdvi_pci_realize()
1599 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE, in amdvi_pci_realize()
1601 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); in amdvi_pci_realize()
1602 pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, in amdvi_pci_realize()
1610 msi_reset(&s->pci.dev); in amdvi_sysbus_reset()
1620 PCIBus *bus = pcms->pcibus; in amdvi_sysbus_realize()
1622 s->iotlb = g_hash_table_new_full(amdvi_uint64_hash, in amdvi_sysbus_realize()
1626 if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { in amdvi_sysbus_realize()
1631 x86ms->ioapic_as = amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVID); in amdvi_sysbus_realize()
1634 memory_region_init_io(&s->mr_mmio, OBJECT(s), &mmio_mem_ops, s, in amdvi_sysbus_realize()
1635 "amdvi-mmio", AMDVI_MMIO_SIZE); in amdvi_sysbus_realize()
1637 &s->mr_mmio); in amdvi_sysbus_realize()
1640 memory_region_init(&s->mr_sys, OBJECT(s), "amdvi-sys", UINT64_MAX); in amdvi_sysbus_realize()
1643 memory_region_init_alias(&s->mr_nodma, OBJECT(s), in amdvi_sysbus_realize()
1644 "amdvi-nodma", get_system_memory(), 0, in amdvi_sysbus_realize()
1646 memory_region_add_subregion_overlap(&s->mr_sys, 0, in amdvi_sysbus_realize()
1647 &s->mr_nodma, 0); in amdvi_sysbus_realize()
1650 memory_region_init_io(&s->mr_ir, OBJECT(s), &amdvi_ir_ops, in amdvi_sysbus_realize()
1651 s, "amdvi-ir", AMDVI_INT_ADDR_SIZE); in amdvi_sysbus_realize()
1652 memory_region_add_subregion_overlap(&s->mr_sys, AMDVI_INT_ADDR_FIRST, in amdvi_sysbus_realize()
1653 &s->mr_ir, 1); in amdvi_sysbus_realize()
1655 if (kvm_enabled() && x86ms->apic_id_limit > 255 && !s->xtsup) { in amdvi_sysbus_realize()
1669 .name = "amd-iommu",
1677 object_initialize(&s->pci, sizeof(s->pci), TYPE_AMD_IOMMU_PCI); in amdvi_sysbus_instance_init()
1686 dc->vmsd = &vmstate_amdvi_sysbus; in amdvi_sysbus_class_init()
1687 dc->hotpluggable = false; in amdvi_sysbus_class_init()
1688 dc_class->realize = amdvi_sysbus_realize; in amdvi_sysbus_class_init()
1689 dc_class->int_remap = amdvi_int_remap; in amdvi_sysbus_class_init()
1690 set_bit(DEVICE_CATEGORY_MISC, dc->categories); in amdvi_sysbus_class_init()
1691 dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device"; in amdvi_sysbus_class_init()
1708 k->vendor_id = PCI_VENDOR_ID_AMD; in amdvi_pci_class_init()
1709 k->device_id = 0x1419; in amdvi_pci_class_init()
1710 k->class_id = 0x0806; in amdvi_pci_class_init()
1711 k->realize = amdvi_pci_realize; in amdvi_pci_class_init()
1713 set_bit(DEVICE_CATEGORY_MISC, dc->categories); in amdvi_pci_class_init()
1714 dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device"; in amdvi_pci_class_init()
1732 imrc->translate = amdvi_translate; in amdvi_iommu_memory_region_class_init()
1733 imrc->notify_flag_changed = amdvi_iommu_notify_flag_changed; in amdvi_iommu_memory_region_class_init()