28 #include "hw/qdev-properties.h"
73     uint64_t bytes = s->chan[ch].next_bytes;  in sifive_pdma_run()
74     uint64_t dst = s->chan[ch].next_dst;  in sifive_pdma_run()
75     uint64_t src = s->chan[ch].next_src;  in sifive_pdma_run()
76     uint32_t config = s->chan[ch].next_config;  in sifive_pdma_run()
112     s->chan[ch].state = DMA_CHAN_STATE_STARTED;  in sifive_pdma_run()
113     s->chan[ch].control &= ~CONTROL_DONE;  in sifive_pdma_run()
114     s->chan[ch].control &= ~CONTROL_ERR;  in sifive_pdma_run()
117     s->chan[ch].exec_config = config;  in sifive_pdma_run()
118     s->chan[ch].exec_bytes = bytes;  in sifive_pdma_run()
119     s->chan[ch].exec_dst = dst;  in sifive_pdma_run()
120     s->chan[ch].exec_src = src;  in sifive_pdma_run()
123         cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);  in sifive_pdma_run()
124         cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);  in sifive_pdma_run()
125         s->chan[ch].exec_src += size;  in sifive_pdma_run()
126         s->chan[ch].exec_dst += size;  in sifive_pdma_run()
127         s->chan[ch].exec_bytes -= size;  in sifive_pdma_run()
131         cpu_physical_memory_read(s->chan[ch].exec_src, buf, remainder);  in sifive_pdma_run()
132         cpu_physical_memory_write(s->chan[ch].exec_dst, buf, remainder);  in sifive_pdma_run()
133         s->chan[ch].exec_src += remainder;  in sifive_pdma_run()
134         s->chan[ch].exec_dst += remainder;  in sifive_pdma_run()
135         s->chan[ch].exec_bytes -= remainder;  in sifive_pdma_run()
139     if (s->chan[ch].next_config & CONFIG_REPEAT) {  in sifive_pdma_run()
140         s->chan[ch].exec_bytes = bytes;  in sifive_pdma_run()
141         s->chan[ch].exec_dst = dst;  in sifive_pdma_run()
142         s->chan[ch].exec_src = src;  in sifive_pdma_run()
147     s->chan[ch].state = DMA_CHAN_STATE_DONE;  in sifive_pdma_run()
148     s->chan[ch].control &= ~CONTROL_RUN;  in sifive_pdma_run()
149     s->chan[ch].control |= CONTROL_DONE;  in sifive_pdma_run()
153     s->chan[ch].state = DMA_CHAN_STATE_ERROR;  in sifive_pdma_run()
154     s->chan[ch].control |= CONTROL_ERR;  in sifive_pdma_run()
162     done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);  in sifive_pdma_update_irq()
163     err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);  in sifive_pdma_update_irq()
165     if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {  in sifive_pdma_update_irq()
166         qemu_irq_raise(s->irq[ch * 2]);  in sifive_pdma_update_irq()
168         qemu_irq_lower(s->irq[ch * 2]);  in sifive_pdma_update_irq()
171     if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {  in sifive_pdma_update_irq()
172         qemu_irq_raise(s->irq[ch * 2 + 1]);  in sifive_pdma_update_irq()
174         qemu_irq_lower(s->irq[ch * 2 + 1]);  in sifive_pdma_update_irq()
177     s->chan[ch].state = DMA_CHAN_STATE_IDLE;  in sifive_pdma_update_irq()
187         val = s->chan[ch].next_bytes;  in sifive_pdma_readq()
190         val = s->chan[ch].next_dst;  in sifive_pdma_readq()
193         val = s->chan[ch].next_src;  in sifive_pdma_readq()
196         val = s->chan[ch].exec_bytes;  in sifive_pdma_readq()
199         val = s->chan[ch].exec_dst;  in sifive_pdma_readq()
202         val = s->chan[ch].exec_src;  in sifive_pdma_readq()
206                       "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n",  in sifive_pdma_readq()
221         val = s->chan[ch].control;  in sifive_pdma_readl()
224         val = s->chan[ch].next_config;  in sifive_pdma_readl()
227         val = extract64(s->chan[ch].next_bytes, 0, 32);  in sifive_pdma_readl()
230         val = extract64(s->chan[ch].next_bytes, 32, 32);  in sifive_pdma_readl()
233         val = extract64(s->chan[ch].next_dst, 0, 32);  in sifive_pdma_readl()
236         val = extract64(s->chan[ch].next_dst, 32, 32);  in sifive_pdma_readl()
239         val = extract64(s->chan[ch].next_src, 0, 32);  in sifive_pdma_readl()
242         val = extract64(s->chan[ch].next_src, 32, 32);  in sifive_pdma_readl()
245         val = s->chan[ch].exec_config;  in sifive_pdma_readl()
248         val = extract64(s->chan[ch].exec_bytes, 0, 32);  in sifive_pdma_readl()
251         val = extract64(s->chan[ch].exec_bytes, 32, 32);  in sifive_pdma_readl()
254         val = extract64(s->chan[ch].exec_dst, 0, 32);  in sifive_pdma_readl()
257         val = extract64(s->chan[ch].exec_dst, 32, 32);  in sifive_pdma_readl()
260         val = extract64(s->chan[ch].exec_src, 0, 32);  in sifive_pdma_readl()
263         val = extract64(s->chan[ch].exec_src, 32, 32);  in sifive_pdma_readl()
267                       "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n",  in sifive_pdma_readl()
309         s->chan[ch].next_bytes = value;  in sifive_pdma_writeq()
312         s->chan[ch].next_dst = value;  in sifive_pdma_writeq()
315         s->chan[ch].next_src = value;  in sifive_pdma_writeq()
320         /* these are read-only registers */  in sifive_pdma_writeq()
324                       "%s: Unexpected 64-bit access to 0x%" HWADDR_PRIX "\n",  in sifive_pdma_writeq()
333     bool claimed, run;  in sifive_pdma_writel()  local
338         claimed = !!(s->chan[ch].control & CONTROL_CLAIM);  in sifive_pdma_writel()
339         run = !!(s->chan[ch].control & CONTROL_RUN);  in sifive_pdma_writel()
343             s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) |  in sifive_pdma_writel()
345             s->chan[ch].next_bytes = 0;  in sifive_pdma_writel()
346             s->chan[ch].next_dst = 0;  in sifive_pdma_writel()
347             s->chan[ch].next_src = 0;  in sifive_pdma_writel()
350         /* claim bit can only be cleared when run is low */  in sifive_pdma_writel()
351         if (run && !(value & CONTROL_CLAIM)) {  in sifive_pdma_writel()
355         s->chan[ch].control = value;  in sifive_pdma_writel()
358          * If channel was not claimed before run bit is set,  in sifive_pdma_writel()
359          * or if the channel is disclaimed when run was low,  in sifive_pdma_writel()
360          * DMA won't run.  in sifive_pdma_writel()
362         if (!claimed || (!run && !(value & CONTROL_CLAIM))) {  in sifive_pdma_writel()
363             s->chan[ch].control &= ~CONTROL_RUN;  in sifive_pdma_writel()
374         s->chan[ch].next_config = value;  in sifive_pdma_writel()
377         s->chan[ch].next_bytes =  in sifive_pdma_writel()
378             deposit64(s->chan[ch].next_bytes, 0, 32, value);  in sifive_pdma_writel()
381         s->chan[ch].next_bytes =  in sifive_pdma_writel()
382             deposit64(s->chan[ch].next_bytes, 32, 32, value);  in sifive_pdma_writel()
385         s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 0, 32, value);  in sifive_pdma_writel()
388         s->chan[ch].next_dst = deposit64(s->chan[ch].next_dst, 32, 32, value);  in sifive_pdma_writel()
391         s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 0, 32, value);  in sifive_pdma_writel()
394         s->chan[ch].next_src = deposit64(s->chan[ch].next_src, 32, 32, value);  in sifive_pdma_writel()
403         /* these are read-only registers */  in sifive_pdma_writel()
407                       "%s: Unexpected 32-bit access to 0x%" HWADDR_PRIX "\n",  in sifive_pdma_writel()
443     /* there are 32-bit and 64-bit wide registers */
459     memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,  in sifive_pdma_realize()
461     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);  in sifive_pdma_realize()
464         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);  in sifive_pdma_realize()
472     dc->desc = "SiFive Platform DMA controller";  in sifive_pdma_class_init()
473     dc->realize = sifive_pdma_realize;  in sifive_pdma_class_init()