Lines Matching full:ch
122 struct omap_dma_channel_s ch[32]; member
143 static void omap_dma_channel_load(struct omap_dma_channel_s *ch) in omap_dma_channel_load() argument
145 struct omap_dma_reg_set_s *a = &ch->active_set; in omap_dma_channel_load()
147 int omap_3_1 = !ch->omap_3_1_compatible_disable; in omap_dma_channel_load()
154 a->src = ch->addr[0]; in omap_dma_channel_load()
155 a->dest = ch->addr[1]; in omap_dma_channel_load()
156 a->frames = ch->frames; in omap_dma_channel_load()
157 a->elements = ch->elements; in omap_dma_channel_load()
158 a->pck_elements = ch->frame_index[!ch->src_sync]; in omap_dma_channel_load()
163 if (unlikely(!ch->elements || !ch->frames)) { in omap_dma_channel_load()
169 switch (ch->mode[i]) { in omap_dma_channel_load()
175 a->elem_delta[i] = ch->data_type; in omap_dma_channel_load()
179 a->elem_delta[i] = ch->data_type + in omap_dma_channel_load()
180 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
184 a->elem_delta[i] = ch->data_type + in omap_dma_channel_load()
185 ch->element_index[omap_3_1 ? 0 : i] - 1; in omap_dma_channel_load()
186 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] - in omap_dma_channel_load()
187 ch->element_index[omap_3_1 ? 0 : i]; in omap_dma_channel_load()
193 normal = !ch->transparent_copy && !ch->constant_fill && in omap_dma_channel_load()
194 /* FIFO is big-endian so either (ch->endian[n] == 1) OR in omap_dma_channel_load()
195 * (ch->endian_lock[n] == 1) mean no endianism conversion. */ in omap_dma_channel_load()
196 (ch->endian[0] | ch->endian_lock[0]) == in omap_dma_channel_load()
197 (ch->endian[1] | ch->endian_lock[1]); in omap_dma_channel_load()
204 ch->dma->type[i] = soc_dma_access_const; in omap_dma_channel_load()
205 else if (a->elem_delta[i] == ch->data_type && normal && in omap_dma_channel_load()
207 ch->dma->type[i] = soc_dma_access_linear; in omap_dma_channel_load()
209 ch->dma->type[i] = soc_dma_access_other; in omap_dma_channel_load()
211 ch->dma->vaddr[i] = ch->addr[i]; in omap_dma_channel_load()
213 soc_dma_ch_update(ch->dma); in omap_dma_channel_load()
217 struct omap_dma_channel_s *ch) in omap_dma_activate_channel() argument
219 if (!ch->active) { in omap_dma_activate_channel()
220 if (ch->set_update) { in omap_dma_activate_channel()
227 omap_dma_channel_load(ch); in omap_dma_activate_channel()
228 ch->set_update = 0; in omap_dma_activate_channel()
231 ch->active = 1; in omap_dma_activate_channel()
232 soc_dma_set_request(ch->dma, 1); in omap_dma_activate_channel()
233 if (ch->sync) in omap_dma_activate_channel()
234 ch->status |= SYNC; in omap_dma_activate_channel()
239 struct omap_dma_channel_s *ch) in omap_dma_deactivate_channel() argument
242 ch->cpc = ch->active_set.dest & 0xffff; in omap_dma_deactivate_channel()
244 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) { in omap_dma_deactivate_channel()
246 ch->pending_request = 0; in omap_dma_deactivate_channel()
252 if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) in omap_dma_deactivate_channel()
255 if (ch->active) { in omap_dma_deactivate_channel()
256 ch->active = 0; in omap_dma_deactivate_channel()
257 ch->status &= ~SYNC; in omap_dma_deactivate_channel()
258 soc_dma_set_request(ch->dma, 0); in omap_dma_deactivate_channel()
263 struct omap_dma_channel_s *ch) in omap_dma_enable_channel() argument
265 if (!ch->enable) { in omap_dma_enable_channel()
266 ch->enable = 1; in omap_dma_enable_channel()
267 ch->waiting_end_prog = 0; in omap_dma_enable_channel()
268 omap_dma_channel_load(ch); in omap_dma_enable_channel()
269 /* TODO: theoretically if ch->sync && ch->prefetch && in omap_dma_enable_channel()
270 * !s->dma->drqbmp[ch->sync], we should also activate and fetch in omap_dma_enable_channel()
272 if ((!ch->sync) || (s->dma->drqbmp & (1ULL << ch->sync))) { in omap_dma_enable_channel()
273 omap_dma_activate_channel(s, ch); in omap_dma_enable_channel()
279 struct omap_dma_channel_s *ch) in omap_dma_disable_channel() argument
281 if (ch->enable) { in omap_dma_disable_channel()
282 ch->enable = 0; in omap_dma_disable_channel()
284 ch->pending_request = 0; in omap_dma_disable_channel()
285 omap_dma_deactivate_channel(s, ch); in omap_dma_disable_channel()
290 struct omap_dma_channel_s *ch) in omap_dma_channel_end_prog() argument
292 if (ch->waiting_end_prog) { in omap_dma_channel_end_prog()
293 ch->waiting_end_prog = 0; in omap_dma_channel_end_prog()
294 if (!ch->sync || ch->pending_request) { in omap_dma_channel_end_prog()
295 ch->pending_request = 0; in omap_dma_channel_end_prog()
296 omap_dma_activate_channel(s, ch); in omap_dma_channel_end_prog()
303 struct omap_dma_channel_s *ch = s->ch; in omap_dma_interrupts_3_1_update() local
306 if (ch[0].status | ch[6].status) in omap_dma_interrupts_3_1_update()
307 qemu_irq_raise(ch[0].irq); in omap_dma_interrupts_3_1_update()
308 if (ch[1].status | ch[7].status) in omap_dma_interrupts_3_1_update()
309 qemu_irq_raise(ch[1].irq); in omap_dma_interrupts_3_1_update()
310 if (ch[2].status | ch[8].status) in omap_dma_interrupts_3_1_update()
311 qemu_irq_raise(ch[2].irq); in omap_dma_interrupts_3_1_update()
312 if (ch[3].status) in omap_dma_interrupts_3_1_update()
313 qemu_irq_raise(ch[3].irq); in omap_dma_interrupts_3_1_update()
314 if (ch[4].status) in omap_dma_interrupts_3_1_update()
315 qemu_irq_raise(ch[4].irq); in omap_dma_interrupts_3_1_update()
316 if (ch[5].status) in omap_dma_interrupts_3_1_update()
317 qemu_irq_raise(ch[5].irq); in omap_dma_interrupts_3_1_update()
322 struct omap_dma_channel_s *ch = s->ch; in omap_dma_interrupts_3_2_update() local
325 for (i = s->chans; i; ch ++, i --) in omap_dma_interrupts_3_2_update()
326 if (ch->status) in omap_dma_interrupts_3_2_update()
327 qemu_irq_raise(ch->irq); in omap_dma_interrupts_3_2_update()
348 struct omap_dma_channel_s *ch = s->ch; in omap_dma_process_request() local
350 for (channel = 0; channel < s->chans; channel ++, ch ++) { in omap_dma_process_request()
351 if (ch->enable && ch->sync == request) { in omap_dma_process_request()
352 if (!ch->active) in omap_dma_process_request()
353 omap_dma_activate_channel(s, ch); in omap_dma_process_request()
354 else if (!ch->pending_request) in omap_dma_process_request()
355 ch->pending_request = 1; in omap_dma_process_request()
359 ch->status |= EVENT_DROP_INTR; in omap_dma_process_request()
372 struct omap_dma_channel_s *ch = dma->opaque; in omap_dma_transfer_generic() local
373 struct omap_dma_reg_set_s *a = &ch->active_set; in omap_dma_transfer_generic()
376 uint16_t status = ch->status; in omap_dma_transfer_generic()
382 if (!ch->constant_fill) in omap_dma_transfer_generic()
383 cpu_physical_memory_read(a->src, value, ch->data_type); in omap_dma_transfer_generic()
385 *(uint32_t *) value = ch->color; in omap_dma_transfer_generic()
387 if (!ch->transparent_copy || *(uint32_t *) value != ch->color) in omap_dma_transfer_generic()
388 cpu_physical_memory_write(a->dest, value, ch->data_type); in omap_dma_transfer_generic()
403 if (!ch->sync) in omap_dma_transfer_generic()
404 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
406 } while ((bytes -= ch->data_type)); in omap_dma_transfer_generic()
409 if (ch->sync && !ch->fs && !ch->bs) in omap_dma_transfer_generic()
410 omap_dma_deactivate_channel(s, ch); in omap_dma_transfer_generic()
414 if (ch->interrupts & LAST_FRAME_INTR) in omap_dma_transfer_generic()
415 ch->status |= LAST_FRAME_INTR; in omap_dma_transfer_generic()
420 if (ch->interrupts & HALF_FRAME_INTR) in omap_dma_transfer_generic()
421 ch->status |= HALF_FRAME_INTR; in omap_dma_transfer_generic()
423 if (ch->fs && ch->bs) { in omap_dma_transfer_generic()
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync) in omap_dma_transfer_generic()
431 ch->status |= END_PKT_INTR; in omap_dma_transfer_generic()
434 if (ch->sync) in omap_dma_transfer_generic()
435 omap_dma_deactivate_channel(s, ch); in omap_dma_transfer_generic()
447 if (ch->sync && ch->fs && !ch->bs) in omap_dma_transfer_generic()
448 omap_dma_deactivate_channel(s, ch); in omap_dma_transfer_generic()
451 if (!ch->sync) in omap_dma_transfer_generic()
452 ch->cpc = a->dest & 0xffff; in omap_dma_transfer_generic()
455 if (ch->interrupts & END_FRAME_INTR) in omap_dma_transfer_generic()
456 ch->status |= END_FRAME_INTR; in omap_dma_transfer_generic()
462 if (ch->omap_3_1_compatible_disable) { in omap_dma_transfer_generic()
463 omap_dma_disable_channel(s, ch); in omap_dma_transfer_generic()
464 if (ch->link_enabled) in omap_dma_transfer_generic()
466 &s->ch[ch->link_next_ch]); in omap_dma_transfer_generic()
468 if (!ch->auto_init) in omap_dma_transfer_generic()
469 omap_dma_disable_channel(s, ch); in omap_dma_transfer_generic()
470 else if (ch->repeat || ch->end_prog) in omap_dma_transfer_generic()
471 omap_dma_channel_load(ch); in omap_dma_transfer_generic()
473 ch->waiting_end_prog = 1; in omap_dma_transfer_generic()
474 omap_dma_deactivate_channel(s, ch); in omap_dma_transfer_generic()
478 if (ch->interrupts & END_BLOCK_INTR) in omap_dma_transfer_generic()
479 ch->status |= END_BLOCK_INTR; in omap_dma_transfer_generic()
482 } while (status == ch->status && ch->active); in omap_dma_transfer_generic()
504 struct omap_dma_channel_s *ch = dma->opaque;
508 a = &ch->active_set;
510 src_p = &s->mpu->port[ch->port[0]];
511 dest_p = &s->mpu->port[ch->port[1]];
512 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
516 if (ch->interrupts & TIMEOUT_INTR)
517 ch->status |= TIMEOUT_INTR;
518 omap_dma_deactivate_channel(s, ch);
539 ch->sync && !ch->fs && !ch->bs,
549 (ch->interrupts & LAST_FRAME_INTR) &&
555 ch->interrupts & HALF_FRAME_INTR,
561 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
565 ch->sync && ch->fs && !ch->bs,
571 ch->fs && ch->bs &&
572 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
576 ch->fs && ch->bs && ch->sync,
587 dma->bytes = min_elems * ch->data_type;
599 omap_dma_deactivate_channel(s, ch);
603 ch->status |= LAST_FRAME_INTR;
608 ch->status |= HALF_FRAME_INTR;
612 ch->status |= END_PKT_INTR;
616 omap_dma_deactivate_channel(s, ch);
620 omap_dma_deactivate_channel(s, ch);
624 ch->status |= END_FRAME_INTR;
630 if (ch->omap_3_1_compatible_disable) {
631 omap_dma_disable_channel(s, ch);
632 if (ch->link_enabled)
633 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
635 if (!ch->auto_init)
636 omap_dma_disable_channel(s, ch);
637 else if (ch->repeat || ch->end_prog)
638 omap_dma_channel_load(ch);
640 ch->waiting_end_prog = 1;
641 omap_dma_deactivate_channel(s, ch);
645 if (ch->interrupts & END_BLOCK_INTR)
646 ch->status |= END_BLOCK_INTR;
650 if (ch->fs && ch->bs) {
669 if (!ch->sync && frames)
670 ch->cpc = a->dest & 0xffff;
699 s->ch[i].suspend = 0;
700 s->ch[i].prefetch = 0;
701 s->ch[i].buf_disable = 0;
702 s->ch[i].src_sync = 0;
703 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
704 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
705 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
706 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
707 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
708 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
709 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
710 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
711 s->ch[i].write_mode = 0;
712 s->ch[i].data_type = 0;
713 s->ch[i].transparent_copy = 0;
714 s->ch[i].constant_fill = 0;
715 s->ch[i].color = 0x00000000;
716 s->ch[i].end_prog = 0;
717 s->ch[i].repeat = 0;
718 s->ch[i].auto_init = 0;
719 s->ch[i].link_enabled = 0;
720 s->ch[i].interrupts = 0x0003;
721 s->ch[i].status = 0;
722 s->ch[i].cstatus = 0;
723 s->ch[i].active = 0;
724 s->ch[i].enable = 0;
725 s->ch[i].sync = 0;
726 s->ch[i].pending_request = 0;
727 s->ch[i].waiting_end_prog = 0;
728 s->ch[i].cpc = 0x0000;
729 s->ch[i].fs = 0;
730 s->ch[i].bs = 0;
731 s->ch[i].omap_3_1_compatible_disable = 0;
732 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
733 s->ch[i].priority = 0;
734 s->ch[i].interleave_disabled = 0;
735 s->ch[i].type = 0;
740 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
744 *value = (ch->burst[1] << 14) |
745 (ch->pack[1] << 13) |
746 (ch->port[1] << 9) |
747 (ch->burst[0] << 7) |
748 (ch->pack[0] << 6) |
749 (ch->port[0] << 2) |
750 (ch->data_type >> 1);
757 *value = ch->omap_3_1_compatible_disable << 10;
758 *value |= (ch->mode[1] << 14) |
759 (ch->mode[0] << 12) |
760 (ch->end_prog << 11) |
761 (ch->repeat << 9) |
762 (ch->auto_init << 8) |
763 (ch->enable << 7) |
764 (ch->priority << 6) |
765 (ch->fs << 5) | ch->sync;
769 *value = ch->interrupts;
773 *value = ch->status;
774 ch->status &= SYNC;
775 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
776 *value |= (ch->sibling->status & 0x3f) << 6;
777 ch->sibling->status &= SYNC;
779 qemu_irq_lower(ch->irq);
783 *value = ch->addr[0] & 0x0000ffff;
787 *value = ch->addr[0] >> 16;
791 *value = ch->addr[1] & 0x0000ffff;
795 *value = ch->addr[1] >> 16;
799 *value = ch->elements;
803 *value = ch->frames;
807 *value = ch->frame_index[0];
811 *value = ch->element_index[0];
815 if (ch->omap_3_1_compatible_disable)
816 *value = ch->active_set.src & 0xffff; /* CSAC */
818 *value = ch->cpc;
822 *value = ch->active_set.dest & 0xffff; /* CDAC */
826 *value = ch->element_index[1];
830 *value = ch->frame_index[1];
834 *value = ch->color & 0xffff;
838 *value = ch->color >> 16;
842 *value = (ch->bs << 2) |
843 (ch->transparent_copy << 1) |
844 ch->constant_fill;
848 *value = (ch->link_enabled << 15) |
849 (ch->link_next_ch & 0xf);
853 *value = (ch->interleave_disabled << 15) |
854 ch->type;
864 struct omap_dma_channel_s *ch, int reg, uint16_t value)
868 ch->burst[1] = (value & 0xc000) >> 14;
869 ch->pack[1] = (value & 0x2000) >> 13;
870 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
871 ch->burst[0] = (value & 0x0180) >> 7;
872 ch->pack[0] = (value & 0x0040) >> 6;
873 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
874 if (ch->port[0] >= __omap_dma_port_last) {
876 __func__, ch->port[0]);
878 if (ch->port[1] >= __omap_dma_port_last) {
880 __func__, ch->port[1]);
882 ch->data_type = 1 << (value & 3);
886 ch->data_type >>= 1;
891 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
892 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
893 ch->end_prog = (value & 0x0800) >> 11;
895 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
896 ch->repeat = (value & 0x0200) >> 9;
897 ch->auto_init = (value & 0x0100) >> 8;
898 ch->priority = (value & 0x0040) >> 6;
899 ch->fs = (value & 0x0020) >> 5;
900 ch->sync = value & 0x001f;
903 omap_dma_enable_channel(s, ch);
905 omap_dma_disable_channel(s, ch);
907 if (ch->end_prog)
908 omap_dma_channel_end_prog(s, ch);
913 ch->interrupts = value & 0x3f;
921 ch->addr[0] &= 0xffff0000;
922 ch->addr[0] |= value;
926 ch->addr[0] &= 0x0000ffff;
927 ch->addr[0] |= (uint32_t) value << 16;
931 ch->addr[1] &= 0xffff0000;
932 ch->addr[1] |= value;
936 ch->addr[1] &= 0x0000ffff;
937 ch->addr[1] |= (uint32_t) value << 16;
941 ch->elements = value;
945 ch->frames = value;
949 ch->frame_index[0] = (int16_t) value;
953 ch->element_index[0] = (int16_t) value;
961 ch->element_index[1] = (int16_t) value;
965 ch->frame_index[1] = (int16_t) value;
969 ch->color &= 0xffff0000;
970 ch->color |= value;
974 ch->color &= 0xffff;
975 ch->color |= (uint32_t)value << 16;
979 ch->bs = (value >> 2) & 0x1;
980 ch->transparent_copy = (value >> 1) & 0x1;
981 ch->constant_fill = value & 0x1;
985 ch->link_enabled = (value >> 15) & 0x1;
987 ch->link_enabled = 0;
988 omap_dma_disable_channel(s, ch);
990 ch->link_next_ch = value & 0x1f;
994 ch->interleave_disabled = (value >> 15) & 0x1;
995 ch->type = value & 0xf;
1453 int reg, ch;
1470 ch = (addr >> 6) & 0x0f;
1471 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1501 int reg, ch;
1518 ch = (addr >> 6) & 0x0f;
1519 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1572 if (s->ch[i].active)
1573 soc_dma_set_request(s->ch[i].dma, on);
1650 s->ch[num_irqs].irq = irqs[num_irqs];
1652 s->ch[i].sibling = &s->ch[i + 6];
1653 s->ch[i + 6].sibling = &s->ch[i];
1656 s->ch[i].dma = &s->dma->ch[i];
1657 s->dma->ch[i].opaque = &s->ch[i];