Lines Matching +full:ext +full:- +full:32 +full:k
29 #include "qemu/main-loop.h"
31 #include "hw/qdev-properties.h"
40 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
41 if (cons >= ARRAY_SIZE((r)->items)) { \
43 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
46 ret = &(r)->items[cons].el; \
51 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
67 QXL_MODE(x_res, y_res, 32, orientation)
109 /* these modes need more than 32 MB video memory */
110 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
111 QXL_MODE_EX(4096, 2160), /* 4k */
113 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
115 QXL_MODE_EX(8192, 4320), /* 8k */
128 trace_qxl_set_guest_bug(qxl->id); in qxl_set_guest_bug()
130 qxl->guest_bug = 1; in qxl_set_guest_bug()
131 if (qxl->guestdebug) { in qxl_set_guest_bug()
134 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id); in qxl_set_guest_bug()
143 qxl->guest_bug = 0; in qxl_clear_guest_bug()
152 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right, in qxl_spice_update_area()
153 area->top, area->bottom); in qxl_spice_update_area()
154 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects, in qxl_spice_update_area()
157 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area, in qxl_spice_update_area()
161 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area, in qxl_spice_update_area()
169 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id); in qxl_spice_destroy_surface_wait_complete()
170 qemu_mutex_lock(&qxl->track_lock); in qxl_spice_destroy_surface_wait_complete()
171 qxl->guest_surfaces.cmds[id] = 0; in qxl_spice_destroy_surface_wait_complete()
172 qxl->guest_surfaces.count--; in qxl_spice_destroy_surface_wait_complete()
173 qemu_mutex_unlock(&qxl->track_lock); in qxl_spice_destroy_surface_wait_complete()
181 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async); in qxl_spice_destroy_surface_wait()
185 cookie->u.surface_id = id; in qxl_spice_destroy_surface_wait()
186 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie); in qxl_spice_destroy_surface_wait()
188 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id); in qxl_spice_destroy_surface_wait()
195 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count, in qxl_spice_flush_surfaces_async()
196 qxl->num_free_res); in qxl_spice_flush_surfaces_async()
197 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, in qxl_spice_flush_surfaces_async()
202 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, in qxl_spice_loadvm_commands() argument
205 trace_qxl_spice_loadvm_commands(qxl->id, ext, count); in qxl_spice_loadvm_commands()
206 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count); in qxl_spice_loadvm_commands()
211 trace_qxl_spice_oom(qxl->id); in qxl_spice_oom()
212 spice_qxl_oom(&qxl->ssd.qxl); in qxl_spice_oom()
217 trace_qxl_spice_reset_memslots(qxl->id); in qxl_spice_reset_memslots()
218 spice_qxl_reset_memslots(&qxl->ssd.qxl); in qxl_spice_reset_memslots()
223 trace_qxl_spice_destroy_surfaces_complete(qxl->id); in qxl_spice_destroy_surfaces_complete()
224 qemu_mutex_lock(&qxl->track_lock); in qxl_spice_destroy_surfaces_complete()
225 memset(qxl->guest_surfaces.cmds, 0, in qxl_spice_destroy_surfaces_complete()
226 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces); in qxl_spice_destroy_surfaces_complete()
227 qxl->guest_surfaces.count = 0; in qxl_spice_destroy_surfaces_complete()
228 qemu_mutex_unlock(&qxl->track_lock); in qxl_spice_destroy_surfaces_complete()
233 trace_qxl_spice_destroy_surfaces(qxl->id, async); in qxl_spice_destroy_surfaces()
235 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, in qxl_spice_destroy_surfaces()
239 spice_qxl_destroy_surfaces(&qxl->ssd.qxl); in qxl_spice_destroy_surfaces()
248 trace_qxl_spice_monitors_config(qxl->id); in qxl_spice_monitors_config_async()
252 * - we are not running yet (post_load), we will assert in qxl_spice_monitors_config_async()
254 * - this is not a guest io, but a reply, so async_io isn't set. in qxl_spice_monitors_config_async()
256 spice_qxl_monitors_config_async(&qxl->ssd.qxl, in qxl_spice_monitors_config_async()
257 qxl->guest_monitors_config, in qxl_spice_monitors_config_async()
264 if (qxl->max_outputs) { in qxl_spice_monitors_config_async()
265 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs); in qxl_spice_monitors_config_async()
268 qxl->guest_monitors_config = qxl->ram->monitors_config; in qxl_spice_monitors_config_async()
269 spice_qxl_monitors_config_async(&qxl->ssd.qxl, in qxl_spice_monitors_config_async()
270 qxl->ram->monitors_config, in qxl_spice_monitors_config_async()
276 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST, in qxl_spice_monitors_config_async()
278 if (cfg != NULL && cfg->count == 1) { in qxl_spice_monitors_config_async()
279 qxl->guest_primary.resized = 1; in qxl_spice_monitors_config_async()
280 qxl->guest_head0_width = cfg->heads[0].width; in qxl_spice_monitors_config_async()
281 qxl->guest_head0_height = cfg->heads[0].height; in qxl_spice_monitors_config_async()
283 qxl->guest_head0_width = 0; in qxl_spice_monitors_config_async()
284 qxl->guest_head0_height = 0; in qxl_spice_monitors_config_async()
290 trace_qxl_spice_reset_image_cache(qxl->id); in qxl_spice_reset_image_cache()
291 spice_qxl_reset_image_cache(&qxl->ssd.qxl); in qxl_spice_reset_image_cache()
296 trace_qxl_spice_reset_cursor(qxl->id); in qxl_spice_reset_cursor()
297 spice_qxl_reset_cursor(&qxl->ssd.qxl); in qxl_spice_reset_cursor()
298 qemu_mutex_lock(&qxl->track_lock); in qxl_spice_reset_cursor()
299 qxl->guest_cursor = 0; in qxl_spice_reset_cursor()
300 qemu_mutex_unlock(&qxl->track_lock); in qxl_spice_reset_cursor()
301 if (qxl->ssd.cursor) { in qxl_spice_reset_cursor()
302 cursor_unref(qxl->ssd.cursor); in qxl_spice_reset_cursor()
304 qxl->ssd.cursor = cursor_builtin_hidden(); in qxl_spice_reset_cursor()
328 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar); in init_qxl_rom()
336 memset(rom, 0, d->rom_size); in init_qxl_rom()
338 rom->magic = cpu_to_le32(QXL_ROM_MAGIC); in init_qxl_rom()
339 rom->id = cpu_to_le32(d->id); in init_qxl_rom()
340 rom->log_level = cpu_to_le32(d->guestdebug); in init_qxl_rom()
341 rom->modes_offset = cpu_to_le32(sizeof(QXLRom)); in init_qxl_rom()
343 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS; in init_qxl_rom()
344 rom->slot_id_bits = MEMSLOT_SLOT_BITS; in init_qxl_rom()
345 rom->slots_start = 1; in init_qxl_rom()
346 rom->slots_end = NUM_MEMSLOTS - 1; in init_qxl_rom()
347 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces); in init_qxl_rom()
351 if (fb > d->vgamem_size) { in init_qxl_rom()
354 modes->modes[n].id = cpu_to_le32(i); in init_qxl_rom()
355 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res); in init_qxl_rom()
356 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res); in init_qxl_rom()
357 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits); in init_qxl_rom()
358 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride); in init_qxl_rom()
359 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili); in init_qxl_rom()
360 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili); in init_qxl_rom()
361 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation); in init_qxl_rom()
364 modes->n_modes = cpu_to_le32(n); in init_qxl_rom()
367 surface0_area_size = ALIGN(d->vgamem_size, 4096); in init_qxl_rom()
368 num_pages = d->vga.vram_size; in init_qxl_rom()
369 num_pages -= ram_header_size; in init_qxl_rom()
370 num_pages -= surface0_area_size; in init_qxl_rom()
373 assert(ram_header_size + surface0_area_size <= d->vga.vram_size); in init_qxl_rom()
375 rom->draw_area_offset = cpu_to_le32(0); in init_qxl_rom()
376 rom->surface0_area_size = cpu_to_le32(surface0_area_size); in init_qxl_rom()
377 rom->pages_offset = cpu_to_le32(surface0_area_size); in init_qxl_rom()
378 rom->num_pages = cpu_to_le32(num_pages); in init_qxl_rom()
379 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size); in init_qxl_rom()
381 if (d->xres && d->yres) { in init_qxl_rom()
383 rom->client_monitors_config.count = 1; in init_qxl_rom()
384 rom->client_monitors_config.heads[0].left = 0; in init_qxl_rom()
385 rom->client_monitors_config.heads[0].top = 0; in init_qxl_rom()
386 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres); in init_qxl_rom()
387 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres); in init_qxl_rom()
388 rom->client_monitors_config_crc = qxl_crc32( in init_qxl_rom()
389 (const uint8_t *)&rom->client_monitors_config, in init_qxl_rom()
390 sizeof(rom->client_monitors_config)); in init_qxl_rom()
393 d->shadow_rom = *rom; in init_qxl_rom()
394 d->rom = rom; in init_qxl_rom()
395 d->modes = modes; in init_qxl_rom()
404 buf = d->vga.vram_ptr; in init_qxl_ram()
405 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset)); in init_qxl_ram()
406 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC); in init_qxl_ram()
407 d->ram->int_pending = cpu_to_le32(0); in init_qxl_ram()
408 d->ram->int_mask = cpu_to_le32(0); in init_qxl_ram()
409 d->ram->update_surface = 0; in init_qxl_ram()
410 d->ram->monitors_config = 0; in init_qxl_ram()
411 SPICE_RING_INIT(&d->ram->cmd_ring); in init_qxl_ram()
412 SPICE_RING_INIT(&d->ram->cursor_ring); in init_qxl_ram()
413 SPICE_RING_INIT(&d->ram->release_ring); in init_qxl_ram()
415 ring = &d->ram->release_ring; in init_qxl_ram()
416 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); in init_qxl_ram()
417 assert(prod < ARRAY_SIZE(ring->items)); in init_qxl_ram()
418 ring->items[prod].el = 0; in init_qxl_ram()
426 memory_region_set_dirty(mr, addr, end - addr); in qxl_set_dirty()
431 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size); in qxl_rom_set_dirty()
437 void *base = qxl->vga.vram_ptr; in qxl_ram_set_dirty()
440 offset = ptr - base; in qxl_ram_set_dirty()
441 assert(offset < qxl->vga.vram_size); in qxl_ram_set_dirty()
442 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3); in qxl_ram_set_dirty()
448 ram_addr_t addr = qxl->shadow_rom.ram_header_offset; in qxl_ring_set_dirty()
449 ram_addr_t end = qxl->vga.vram_size; in qxl_ring_set_dirty()
450 qxl_set_dirty(&qxl->vga.vram, addr, end); in qxl_ring_set_dirty()
457 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext) in qxl_track_command() argument
459 switch (le32_to_cpu(ext->cmd.type)) { in qxl_track_command()
462 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id, in qxl_track_command()
468 uint32_t id = le32_to_cpu(cmd->surface_id); in qxl_track_command()
470 if (id >= qxl->ssd.num_surfaces) { in qxl_track_command()
472 qxl->ssd.num_surfaces); in qxl_track_command()
475 if (cmd->type == QXL_SURFACE_CMD_CREATE && in qxl_track_command()
476 (cmd->u.surface_create.stride & 0x03) != 0) { in qxl_track_command()
478 cmd->u.surface_create.stride); in qxl_track_command()
481 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) { in qxl_track_command()
482 if (cmd->type == QXL_SURFACE_CMD_CREATE) { in qxl_track_command()
483 qxl->guest_surfaces.cmds[id] = ext->cmd.data; in qxl_track_command()
484 qxl->guest_surfaces.count++; in qxl_track_command()
485 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) { in qxl_track_command()
486 qxl->guest_surfaces.max = qxl->guest_surfaces.count; in qxl_track_command()
489 if (cmd->type == QXL_SURFACE_CMD_DESTROY) { in qxl_track_command()
490 qxl->guest_surfaces.cmds[id] = 0; in qxl_track_command()
491 qxl->guest_surfaces.count--; in qxl_track_command()
498 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id, in qxl_track_command()
504 if (cmd->type == QXL_CURSOR_SET) { in qxl_track_command()
505 qemu_mutex_lock(&qxl->track_lock); in qxl_track_command()
506 qxl->guest_cursor = ext->cmd.data; in qxl_track_command()
507 qemu_mutex_unlock(&qxl->track_lock); in qxl_track_command()
509 if (cmd->type == QXL_CURSOR_HIDE) { in qxl_track_command()
510 qemu_mutex_lock(&qxl->track_lock); in qxl_track_command()
511 qxl->guest_cursor = 0; in qxl_track_command()
512 qemu_mutex_unlock(&qxl->track_lock); in qxl_track_command()
526 trace_qxl_interface_attach_worker(qxl->id); in interface_attached_worker()
540 trace_qxl_interface_set_compression_level(qxl->id, level); in interface_set_compression_level()
541 qxl->shadow_rom.compression_level = cpu_to_le32(level); in interface_set_compression_level()
542 qxl->rom->compression_level = cpu_to_le32(level); in interface_set_compression_level()
550 trace_qxl_interface_get_init_info(qxl->id); in interface_get_init_info()
551 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS; in interface_get_init_info()
552 info->memslot_id_bits = MEMSLOT_SLOT_BITS; in interface_get_init_info()
553 info->num_memslots = NUM_MEMSLOTS; in interface_get_init_info()
554 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS; in interface_get_init_info()
555 info->internal_groupslot_id = 0; in interface_get_init_info()
556 info->qxl_ram_size = in interface_get_init_info()
557 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS; in interface_get_init_info()
558 info->n_surfaces = qxl->ssd.num_surfaces; in interface_get_init_info()
613 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext) in interface_get_command() argument
621 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode)); in interface_get_command()
623 switch (qxl->mode) { in interface_get_command()
626 qemu_mutex_lock(&qxl->ssd.lock); in interface_get_command()
627 update = QTAILQ_FIRST(&qxl->ssd.updates); in interface_get_command()
629 QTAILQ_REMOVE(&qxl->ssd.updates, update, next); in interface_get_command()
630 *ext = update->ext; in interface_get_command()
633 qemu_mutex_unlock(&qxl->ssd.lock); in interface_get_command()
635 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); in interface_get_command()
636 qxl_log_command(qxl, "vga", ext); in interface_get_command()
642 ring = &qxl->ram->cmd_ring; in interface_get_command()
643 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) { in interface_get_command()
650 ext->cmd = *cmd; in interface_get_command()
651 ext->group_id = MEMSLOT_GROUP_GUEST; in interface_get_command()
652 ext->flags = qxl->cmdflags; in interface_get_command()
658 qxl->guest_primary.commands++; in interface_get_command()
659 qxl_track_command(qxl, ext); in interface_get_command()
660 qxl_log_command(qxl, "cmd", ext); in interface_get_command()
661 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode)); in interface_get_command()
674 trace_qxl_ring_command_req_notification(qxl->id); in interface_req_cmd_notification()
675 switch (qxl->mode) { in interface_req_cmd_notification()
679 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait); in interface_req_cmd_notification()
692 QXLReleaseRing *ring = &d->ram->release_ring; in qxl_push_free_res()
696 #define QXL_FREE_BUNCH_SIZE 32 in qxl_push_free_res()
698 if (ring->prod - ring->cons + 1 == ring->num_items) { in qxl_push_free_res()
699 /* ring full -- can't push */ in qxl_push_free_res()
702 if (!flush && d->oom_running) { in qxl_push_free_res()
706 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) { in qxl_push_free_res()
712 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode), in qxl_push_free_res()
713 d->guest_surfaces.count, d->num_free_res, in qxl_push_free_res()
714 d->last_release, notify ? "yes" : "no"); in qxl_push_free_res()
715 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons, in qxl_push_free_res()
716 ring->num_items, ring->prod, ring->cons); in qxl_push_free_res()
721 ring = &d->ram->release_ring; in qxl_push_free_res()
722 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); in qxl_push_free_res()
723 if (prod >= ARRAY_SIZE(ring->items)) { in qxl_push_free_res()
725 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); in qxl_push_free_res()
728 ring->items[prod].el = 0; in qxl_push_free_res()
729 d->num_free_res = 0; in qxl_push_free_res()
730 d->last_release = NULL; in qxl_push_free_res()
736 QXLReleaseInfoExt ext) in interface_release_resource() argument
743 if (!ext.info) { in interface_release_resource()
746 if (ext.group_id == MEMSLOT_GROUP_HOST) { in interface_release_resource()
747 /* host group -> vga mode update request */ in interface_release_resource()
748 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id); in interface_release_resource()
750 g_assert(cmdext->cmd.type == QXL_CMD_DRAW); in interface_release_resource()
751 update = container_of(cmdext, SimpleSpiceUpdate, ext); in interface_release_resource()
752 qemu_spice_destroy_update(&qxl->ssd, update); in interface_release_resource()
757 * ext->info points into guest-visible memory in interface_release_resource()
760 ring = &qxl->ram->release_ring; in interface_release_resource()
761 prod = ring->prod & SPICE_RING_INDEX_MASK(ring); in interface_release_resource()
762 if (prod >= ARRAY_SIZE(ring->items)) { in interface_release_resource()
764 "%u >= %zu", prod, ARRAY_SIZE(ring->items)); in interface_release_resource()
767 if (ring->items[prod].el == 0) { in interface_release_resource()
769 id = ext.info->id; in interface_release_resource()
770 ext.info->next = 0; in interface_release_resource()
771 qxl_ram_set_dirty(qxl, &ext.info->next); in interface_release_resource()
772 ring->items[prod].el = id; in interface_release_resource()
776 qxl->last_release->next = ext.info->id; in interface_release_resource()
777 qxl_ram_set_dirty(qxl, &qxl->last_release->next); in interface_release_resource()
778 ext.info->next = 0; in interface_release_resource()
779 qxl_ram_set_dirty(qxl, &ext.info->next); in interface_release_resource()
781 qxl->last_release = ext.info; in interface_release_resource()
782 qxl->num_free_res++; in interface_release_resource()
783 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res); in interface_release_resource()
788 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext) in interface_get_cursor_command() argument
795 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode)); in interface_get_cursor_command()
797 switch (qxl->mode) { in interface_get_cursor_command()
801 ring = &qxl->ram->cursor_ring; in interface_get_cursor_command()
809 ext->cmd = *cmd; in interface_get_cursor_command()
810 ext->group_id = MEMSLOT_GROUP_GUEST; in interface_get_cursor_command()
811 ext->flags = qxl->cmdflags; in interface_get_cursor_command()
817 qxl->guest_primary.commands++; in interface_get_cursor_command()
818 qxl_track_command(qxl, ext); in interface_get_cursor_command()
819 qxl_log_command(qxl, "csr", ext); in interface_get_cursor_command()
820 if (qxl->have_vga) { in interface_get_cursor_command()
821 qxl_render_cursor(qxl, ext); in interface_get_cursor_command()
823 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode)); in interface_get_cursor_command()
836 trace_qxl_ring_cursor_req_notification(qxl->id); in interface_req_cursor_notification()
837 switch (qxl->mode) { in interface_req_cursor_notification()
841 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait); in interface_req_cursor_notification()
855 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in in interface_notify_update()
856 * use by xf86-video-qxl and is defined out in the qxl windows driver. in interface_notify_update()
869 ret = qxl->num_free_res; in interface_flush_resources()
883 qemu_mutex_lock(&qxl->async_lock); in interface_async_complete_io()
884 current_async = qxl->current_async; in interface_async_complete_io()
885 qxl->current_async = QXL_UNDEFINED_IO; in interface_async_complete_io()
886 qemu_mutex_unlock(&qxl->async_lock); in interface_async_complete_io()
888 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie); in interface_async_complete_io()
893 if (cookie && current_async != cookie->io) { in interface_async_complete_io()
896 PRId64 " = cookie->io\n", __func__, current_async, cookie->io); in interface_async_complete_io()
912 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id); in interface_async_complete_io()
930 QEMU_LOCK_GUARD(&qxl->ssd.lock); in interface_update_area_complete()
932 !qxl->render_update_cookie_num) { in interface_update_area_complete()
935 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left, in interface_update_area_complete()
936 dirty->right, dirty->top, dirty->bottom); in interface_update_area_complete()
937 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects); in interface_update_area_complete()
938 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) { in interface_update_area_complete()
940 * overflow - treat this as a full update. Not expected to be common. in interface_update_area_complete()
942 trace_qxl_interface_update_area_complete_overflow(qxl->id, in interface_update_area_complete()
944 qxl->guest_primary.resized = 1; in interface_update_area_complete()
946 if (qxl->guest_primary.resized) { in interface_update_area_complete()
953 qxl_i = qxl->num_dirty_rects; in interface_update_area_complete()
955 qxl->dirty[qxl_i++] = dirty[i]; in interface_update_area_complete()
957 qxl->num_dirty_rects += num_updated_rects; in interface_update_area_complete()
958 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id, in interface_update_area_complete()
959 qxl->num_dirty_rects); in interface_update_area_complete()
960 qemu_bh_schedule(qxl->update_area_bh); in interface_update_area_complete()
969 switch (cookie->type) { in interface_async_complete()
981 __func__, cookie->type); in interface_async_complete()
993 if (qxl->revision < 4) { in interface_set_client_capabilities()
994 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id, in interface_set_client_capabilities()
995 qxl->revision); in interface_set_client_capabilities()
1004 qxl->shadow_rom.client_present = client_present; in interface_set_client_capabilities()
1005 memcpy(qxl->shadow_rom.client_capabilities, caps, in interface_set_client_capabilities()
1006 sizeof(qxl->shadow_rom.client_capabilities)); in interface_set_client_capabilities()
1007 qxl->rom->client_present = client_present; in interface_set_client_capabilities()
1008 memcpy(qxl->rom->client_capabilities, caps, in interface_set_client_capabilities()
1009 sizeof(qxl->rom->client_capabilities)); in interface_set_client_capabilities()
1022 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs); in qxl_rom_monitors_config_changed()
1024 if (rom->client_monitors_config.count != monitors_count) { in qxl_rom_monitors_config_changed()
1028 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { in qxl_rom_monitors_config_changed()
1029 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; in qxl_rom_monitors_config_changed()
1030 QXLURect *rect = &rom->client_monitors_config.heads[i]; in qxl_rom_monitors_config_changed()
1031 /* monitor->depth ignored */ in qxl_rom_monitors_config_changed()
1032 if ((rect->left != monitor->x) || in qxl_rom_monitors_config_changed()
1033 (rect->top != monitor->y) || in qxl_rom_monitors_config_changed()
1034 (rect->right != monitor->x + monitor->width) || in qxl_rom_monitors_config_changed()
1035 (rect->bottom != monitor->y + monitor->height)) { in qxl_rom_monitors_config_changed()
1048 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar); in interface_client_monitors_config()
1050 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads); in interface_client_monitors_config()
1053 if (qxl->revision < 4) { in interface_client_monitors_config()
1054 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id, in interface_client_monitors_config()
1055 qxl->revision); in interface_client_monitors_config()
1064 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 || in interface_client_monitors_config()
1065 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) { in interface_client_monitors_config()
1066 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id, in interface_client_monitors_config()
1067 qxl->ram->int_mask, in interface_client_monitors_config()
1076 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) { in interface_client_monitors_config()
1077 max_outputs = qxl->max_outputs; in interface_client_monitors_config()
1084 memset(&rom->client_monitors_config, 0, in interface_client_monitors_config()
1085 sizeof(rom->client_monitors_config)); in interface_client_monitors_config()
1086 rom->client_monitors_config.count = monitors_config->num_of_monitors; in interface_client_monitors_config()
1087 /* monitors_config->flags ignored */ in interface_client_monitors_config()
1088 if (rom->client_monitors_config.count >= max_outputs) { in interface_client_monitors_config()
1089 trace_qxl_client_monitors_config_capped(qxl->id, in interface_client_monitors_config()
1090 monitors_config->num_of_monitors, in interface_client_monitors_config()
1092 rom->client_monitors_config.count = max_outputs; in interface_client_monitors_config()
1094 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) { in interface_client_monitors_config()
1095 VDAgentMonConfig *monitor = &monitors_config->monitors[i]; in interface_client_monitors_config()
1096 QXLURect *rect = &rom->client_monitors_config.heads[i]; in interface_client_monitors_config()
1097 /* monitor->depth ignored */ in interface_client_monitors_config()
1098 rect->left = monitor->x; in interface_client_monitors_config()
1099 rect->top = monitor->y; in interface_client_monitors_config()
1100 rect->right = monitor->x + monitor->width; in interface_client_monitors_config()
1101 rect->bottom = monitor->y + monitor->height; in interface_client_monitors_config()
1103 rom->client_monitors_config_crc = qxl_crc32( in interface_client_monitors_config()
1104 (const uint8_t *)&rom->client_monitors_config, in interface_client_monitors_config()
1105 sizeof(rom->client_monitors_config)); in interface_client_monitors_config()
1106 trace_qxl_client_monitors_config_crc(qxl->id, in interface_client_monitors_config()
1107 sizeof(rom->client_monitors_config), in interface_client_monitors_config()
1108 rom->client_monitors_config_crc); in interface_client_monitors_config()
1110 trace_qxl_interrupt_client_monitors_config(qxl->id, in interface_client_monitors_config()
1111 rom->client_monitors_config.count, in interface_client_monitors_config()
1112 rom->client_monitors_config.heads); in interface_client_monitors_config()
1155 if (d->mode == QXL_MODE_VGA) { in qxl_enter_vga_mode()
1158 trace_qxl_enter_vga_mode(d->id); in qxl_enter_vga_mode()
1159 spice_qxl_driver_unload(&d->ssd.qxl); in qxl_enter_vga_mode()
1160 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga); in qxl_enter_vga_mode()
1161 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT); in qxl_enter_vga_mode()
1162 qemu_spice_create_host_primary(&d->ssd); in qxl_enter_vga_mode()
1163 d->mode = QXL_MODE_VGA; in qxl_enter_vga_mode()
1164 qemu_spice_display_switch(&d->ssd, d->ssd.ds); in qxl_enter_vga_mode()
1165 vga_dirty_log_start(&d->vga); in qxl_enter_vga_mode()
1166 graphic_hw_update(d->vga.con); in qxl_enter_vga_mode()
1171 if (d->mode != QXL_MODE_VGA) { in qxl_exit_vga_mode()
1174 trace_qxl_exit_vga_mode(d->id); in qxl_exit_vga_mode()
1175 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d); in qxl_exit_vga_mode()
1176 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE); in qxl_exit_vga_mode()
1177 vga_dirty_log_stop(&d->vga); in qxl_exit_vga_mode()
1183 uint32_t pending = le32_to_cpu(d->ram->int_pending); in qxl_update_irq()
1184 uint32_t mask = le32_to_cpu(d->ram->int_mask); in qxl_update_irq()
1186 pci_set_irq(&d->pci, level); in qxl_update_irq()
1192 QXLRam *ram = d->ram; in qxl_check_state()
1193 int spice_display_running = qemu_spice_display_is_running(&d->ssd); in qxl_check_state()
1195 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring)); in qxl_check_state()
1196 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring)); in qxl_check_state()
1201 QXLRom *rom = d->rom; in qxl_reset_state()
1204 d->shadow_rom.update_id = cpu_to_le32(0); in qxl_reset_state()
1205 *rom = d->shadow_rom; in qxl_reset_state()
1208 d->num_free_res = 0; in qxl_reset_state()
1209 d->last_release = NULL; in qxl_reset_state()
1210 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty)); in qxl_reset_state()
1216 trace_qxl_soft_reset(d->id); in qxl_soft_reset()
1219 qemu_mutex_lock(&d->async_lock); in qxl_soft_reset()
1220 d->current_async = QXL_UNDEFINED_IO; in qxl_soft_reset()
1221 qemu_mutex_unlock(&d->async_lock); in qxl_soft_reset()
1223 if (d->have_vga) { in qxl_soft_reset()
1226 d->mode = QXL_MODE_UNDEFINED; in qxl_soft_reset()
1232 bool startstop = qemu_spice_display_is_running(&d->ssd); in qxl_hard_reset()
1234 trace_qxl_hard_reset(d->id, loadvm); in qxl_hard_reset()
1251 qemu_spice_create_host_memslot(&d->ssd); in qxl_hard_reset()
1271 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val); in qxl_vga_ioport_write()
1272 if (qxl->mode != QXL_MODE_VGA && in qxl_vga_ioport_write()
1273 qxl->revision <= QXL_REVISION_STABLE_V12) { in qxl_vga_ioport_write()
1304 int pci_region = -1; in qxl_add_memslot()
1312 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start); in qxl_add_memslot()
1313 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end); in qxl_add_memslot()
1315 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end); in qxl_add_memslot()
1330 pci_start = d->pci.io_regions[pci_region].addr; in qxl_add_memslot()
1331 pci_end = pci_start + d->pci.io_regions[pci_region].size; in qxl_add_memslot()
1333 if (pci_start == -1) { in qxl_add_memslot()
1354 mr = &d->vga.vram; in qxl_add_memslot()
1358 mr = &d->vram_bar; in qxl_add_memslot()
1365 assert(guest_end - pci_start <= memory_region_size(mr)); in qxl_add_memslot()
1370 memslot.virt_start = virt_start + (guest_start - pci_start); in qxl_add_memslot()
1371 memslot.virt_end = virt_start + (guest_end - pci_start); in qxl_add_memslot()
1372 memslot.addr_delta = memslot.virt_start - delta; in qxl_add_memslot()
1373 memslot.generation = d->rom->slot_generation = 0; in qxl_add_memslot()
1376 qemu_spice_add_memslot(&d->ssd, &memslot, async); in qxl_add_memslot()
1377 d->guest_slots[slot_id].mr = mr; in qxl_add_memslot()
1378 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start; in qxl_add_memslot()
1379 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start; in qxl_add_memslot()
1380 d->guest_slots[slot_id].delta = delta; in qxl_add_memslot()
1381 d->guest_slots[slot_id].active = 1; in qxl_add_memslot()
1387 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id); in qxl_del_memslot()
1388 d->guest_slots[slot_id].active = 0; in qxl_del_memslot()
1394 memset(&d->guest_slots, 0, sizeof(d->guest_slots)); in qxl_reset_memslots()
1399 trace_qxl_reset_surfaces(d->id); in qxl_reset_surfaces()
1400 d->mode = QXL_MODE_UNDEFINED; in qxl_reset_surfaces()
1410 uint32_t slot = (phys >> (64 - 8)) & 0xff; in qxl_get_check_slot_offset()
1419 if (!qxl->guest_slots[slot].active) { in qxl_get_check_slot_offset()
1423 if (offset < qxl->guest_slots[slot].delta) { in qxl_get_check_slot_offset()
1426 slot, offset, qxl->guest_slots[slot].delta); in qxl_get_check_slot_offset()
1429 offset -= qxl->guest_slots[slot].delta; in qxl_get_check_slot_offset()
1430 if (offset > qxl->guest_slots[slot].size) { in qxl_get_check_slot_offset()
1433 slot, offset, qxl->guest_slots[slot].size); in qxl_get_check_slot_offset()
1436 size_available = memory_region_size(qxl->guest_slots[slot].mr); in qxl_get_check_slot_offset()
1437 if (qxl->guest_slots[slot].offset + offset >= size_available) { in qxl_get_check_slot_offset()
1440 slot, qxl->guest_slots[slot].offset + offset, in qxl_get_check_slot_offset()
1444 size_available -= qxl->guest_slots[slot].offset + offset; in qxl_get_check_slot_offset()
1450 size_requested - size_available); in qxl_get_check_slot_offset()
1475 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr); in qxl_phys2virt()
1476 ptr += qxl->guest_slots[slot].offset; in qxl_phys2virt()
1493 QXLSurfaceCreate *sc = &qxl->guest_primary.surface; in qxl_create_guest_primary()
1494 uint32_t requested_height = le32_to_cpu(sc->height); in qxl_create_guest_primary()
1495 int requested_stride = le32_to_cpu(sc->stride); in qxl_create_guest_primary()
1499 > qxl->vgamem_size) { in qxl_create_guest_primary()
1503 qxl->vgamem_size); in qxl_create_guest_primary()
1507 if (qxl->mode == QXL_MODE_NATIVE) { in qxl_create_guest_primary()
1513 surface.format = le32_to_cpu(sc->format); in qxl_create_guest_primary()
1514 surface.height = le32_to_cpu(sc->height); in qxl_create_guest_primary()
1515 surface.mem = le64_to_cpu(sc->mem); in qxl_create_guest_primary()
1516 surface.position = le32_to_cpu(sc->position); in qxl_create_guest_primary()
1517 surface.stride = le32_to_cpu(sc->stride); in qxl_create_guest_primary()
1518 surface.width = le32_to_cpu(sc->width); in qxl_create_guest_primary()
1519 surface.type = le32_to_cpu(sc->type); in qxl_create_guest_primary()
1520 surface.flags = le32_to_cpu(sc->flags); in qxl_create_guest_primary()
1521 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem, in qxl_create_guest_primary()
1522 sc->format, sc->position); in qxl_create_guest_primary()
1523 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type, in qxl_create_guest_primary()
1524 sc->flags); in qxl_create_guest_primary()
1538 qxl->mode = QXL_MODE_NATIVE; in qxl_create_guest_primary()
1539 qxl->cmdflags = 0; in qxl_create_guest_primary()
1540 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async); in qxl_create_guest_primary()
1551 if (d->mode == QXL_MODE_UNDEFINED) { in qxl_destroy_primary()
1554 trace_qxl_destroy_primary(d->id); in qxl_destroy_primary()
1555 d->mode = QXL_MODE_UNDEFINED; in qxl_destroy_primary()
1556 qemu_spice_destroy_primary_surface(&d->ssd, 0, async); in qxl_destroy_primary()
1563 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; in qxl_set_mode()
1564 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start; in qxl_set_mode()
1565 QXLMode *mode = d->modes->modes + modenr; in qxl_set_mode()
1566 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr; in qxl_set_mode()
1572 if (modenr >= d->modes->n_modes) { in qxl_set_mode()
1578 .width = mode->x_res, in qxl_set_mode()
1579 .height = mode->y_res, in qxl_set_mode()
1580 .stride = -mode->x_res * 4, in qxl_set_mode()
1584 .mem = devmem + d->shadow_rom.draw_area_offset, in qxl_set_mode()
1587 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits, in qxl_set_mode()
1593 d->guest_slots[0].slot = slot; in qxl_set_mode()
1599 d->guest_primary.surface = surface; in qxl_set_mode()
1602 d->mode = QXL_MODE_COMPAT; in qxl_set_mode()
1603 d->cmdflags = QXL_COMMAND_FLAG_COMPAT; in qxl_set_mode()
1604 if (mode->bits == 16) { in qxl_set_mode()
1605 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP; in qxl_set_mode()
1607 d->shadow_rom.mode = cpu_to_le32(modenr); in qxl_set_mode()
1608 d->rom->mode = cpu_to_le32(modenr); in qxl_set_mode()
1620 if (d->guest_bug && io_port != QXL_IO_RESET) {
1624 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1627 io_port, d->revision);
1643 if (d->mode != QXL_MODE_VGA) {
1646 trace_qxl_io_unexpected_vga_mode(d->id,
1681 WITH_QEMU_LOCK_GUARD(&d->async_lock) {
1682 if (d->current_async != QXL_UNDEFINED_IO) {
1684 io_port, d->current_async);
1687 d->current_async = orig_io_port;
1693 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1701 QXLRect update = d->ram->update_area;
1703 if (d->ram->update_surface > d->ssd.num_surfaces) {
1705 d->ram->update_surface);
1723 cookie->u.area = update;
1725 qxl_spice_update_area(d, d->ram->update_surface,
1726 cookie ? &cookie->u.area : &update,
1731 qemu_spice_wakeup(&d->ssd);
1734 qemu_spice_wakeup(&d->ssd);
1740 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1743 d->oom_running = 1;
1745 d->oom_running = 0;
1759 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) {
1761 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1762 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1763 sizeof(d->ram->log_buf));
1764 trace_qxl_io_log(d->id, log_buf);
1765 if (d->guestdebug) {
1766 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1780 if (d->guest_slots[val].active) {
1785 d->guest_slots[val].slot = d->ram->mem_slot;
1801 d->guest_primary.surface = d->ram->create_surface;
1811 trace_qxl_io_destroy_primary_ignored(d->id,
1812 qxl_mode_to_string(d->mode));
1817 if (val >= d->ssd.num_surfaces) {
1825 QXLReleaseRing *ring = &d->ram->release_ring;
1826 if (ring->prod - ring->cons + 1 == ring->num_items) {
1829 ring->prod, ring->cons);
1838 d->mode = QXL_MODE_UNDEFINED;
1851 qemu_mutex_lock(&d->async_lock);
1852 d->current_async = QXL_UNDEFINED_IO;
1853 qemu_mutex_unlock(&d->async_lock);
1862 trace_qxl_io_read_unexpected(qxl->id);
1886 trace_qxl_send_events(d->id, events);
1887 if (!qemu_spice_display_is_running(&d->ssd)) {
1888 /* spice-server tracks guest running state and should not do this */
1889 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1891 trace_qxl_send_events_vm_stopped(d->id, events);
1897 * thus warn that qatomic_fetch_or(&d->ram->int_pending, ...)
1899 * out-of-line call for it, which results in a link error since
1902 * In fact we set up d->ram in init_qxl_ram() so it always starts
1903 * at a 4K boundary, so we know that &d->ram->int_pending is
1917 old_pending = qatomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1922 qemu_bh_schedule(d->update_irq);
1944 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1945 qxl_set_dirty(qxl->guest_slots[slot].mr,
1946 qxl->guest_slots[slot].offset + offset,
1947 qxl->guest_slots[slot].offset + offset + size);
1954 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1959 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1960 qxl->guest_primary.surface.height,
1961 qxl->guest_primary.surface.stride);
1963 /* dirty the off-screen surfaces */
1964 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1967 if (qxl->guest_surfaces.cmds[i] == 0) {
1971 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1974 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1975 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1976 cmd->u.surface_create.height,
1977 cmd->u.surface_create.stride);
2006 if (qxl->mode == QXL_MODE_VGA) {
2007 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2016 qxl->ssd.ds = surface;
2017 if (qxl->mode == QXL_MODE_VGA) {
2018 qemu_spice_display_switch(&qxl->ssd, surface);
2026 if (qxl->mode == QXL_MODE_VGA) {
2027 qemu_spice_display_refresh(&qxl->ssd);
2041 if (qxl->vgamem_size_mb < 8) {
2042 qxl->vgamem_size_mb = 8;
2045 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2047 if (qxl->vgamem_size_mb > 256) {
2048 qxl->vgamem_size_mb = 256;
2050 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2053 if (qxl->ram_size_mb != -1) {
2054 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2056 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2057 qxl->vga.vram_size = qxl->vgamem_size * 2;
2060 /* vram32 (surfaces, 32bit, bar 1) */
2061 if (qxl->vram32_size_mb != -1) {
2062 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2064 if (qxl->vram32_size < 4096) {
2065 qxl->vram32_size = 4096;
2069 if (qxl->vram_size_mb != -1) {
2070 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2072 if (qxl->vram_size < qxl->vram32_size) {
2073 qxl->vram_size = qxl->vram32_size;
2076 if (qxl->revision == 1) {
2077 qxl->vram32_size = 4096;
2078 qxl->vram_size = 4096;
2080 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2081 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2082 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2083 qxl->vram_size = pow2ceil(qxl->vram_size);
2088 uint8_t* config = qxl->pci.config;
2092 qemu_spice_display_init_common(&qxl->ssd);
2093 qxl->mode = QXL_MODE_UNDEFINED;
2094 qxl->num_memslots = NUM_MEMSLOTS;
2095 qemu_mutex_init(&qxl->track_lock);
2096 qemu_mutex_init(&qxl->async_lock);
2097 qxl->current_async = QXL_UNDEFINED_IO;
2098 qxl->guest_bug = 0;
2100 switch (qxl->revision) {
2101 case 1: /* spice 0.4 -- qxl-1 */
2105 case 2: /* spice 0.6 -- qxl-2 */
2109 case 3: /* qxl-3 */
2111 io_size = 32; /* PCI region size must be pow2 */
2113 case 4: /* qxl-4 */
2117 case 5: /* qxl-5 */
2123 qxl->revision, QXL_DEFAULT_REVISION);
2130 qxl->rom_size = qxl_rom_size();
2131 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2132 qxl->rom_size, &error_fatal);
2136 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2137 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2138 qxl->vram_size, &error_fatal);
2139 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2140 &qxl->vram_bar, 0, qxl->vram32_size);
2142 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2143 "qxl-ioports", io_size);
2144 if (qxl->have_vga) {
2145 vga_dirty_log_start(&qxl->vga);
2147 memory_region_set_flush_coalesced(&qxl->io_bar);
2150 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2151 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2153 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2154 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2156 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2157 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2159 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2160 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2162 if (qxl->vram32_size < qxl->vram_size) {
2165 * configured to be larger than the 32bit vram bar.
2167 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2171 &qxl->vram_bar);
2176 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2177 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2178 qxl->vram32_size / MiB);
2180 qxl->vram_size / MiB,
2181 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2183 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2184 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2185 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2193 if (qemu_console_fill_device_address(qxl->vga.con,
2196 spice_qxl_set_device_info(&qxl->ssd.qxl,
2199 qxl->max_outputs);
2207 qxl->update_irq = qemu_bh_new_guarded(qxl_update_irq_bh, qxl,
2208 &DEVICE(qxl)->mem_reentrancy_guard);
2211 qxl->update_area_bh = qemu_bh_new_guarded(qxl_render_update_area_bh, qxl,
2212 &DEVICE(qxl)->mem_reentrancy_guard);
2213 qxl->ssd.cursor_bh = qemu_bh_new_guarded(qemu_spice_cursor_refresh_bh, &qxl->ssd,
2214 &DEVICE(qxl)->mem_reentrancy_guard);
2220 VGACommonState *vga = &qxl->vga;
2224 vga->vbe_size = qxl->vgamem_size;
2225 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2233 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2235 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2236 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2237 qxl->have_vga = true;
2239 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2240 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2241 if (qxl->id != 0) {
2242 error_setg(errp, "primary qxl-vga device must be console 0 "
2253 qxl->ssd.dcl.ops = &display_listener_ops;
2254 qxl->ssd.dcl.con = vga->con;
2255 register_displaychangelistener(&qxl->ssd.dcl);
2263 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2264 qxl->vga.vram_size, &error_fatal);
2265 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2266 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2267 qxl->ssd.dcl.con = qxl->vga.con;
2268 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2276 uint8_t *ram_start = d->vga.vram_ptr;
2278 trace_qxl_pre_save(d->id);
2279 if (d->last_release == NULL) {
2280 d->last_release_offset = 0;
2282 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2284 if (d->last_release_offset >= d->vga.vram_size) {
2295 trace_qxl_pre_load(d->id);
2306 if (!d->guest_slots[i].active) {
2316 uint8_t *ram_start = d->vga.vram_ptr;
2320 assert(d->last_release_offset < d->vga.vram_size);
2321 if (d->last_release_offset == 0) {
2322 d->last_release = NULL;
2324 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2327 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2329 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2330 newmode = d->mode;
2331 d->mode = QXL_MODE_UNDEFINED;
2345 /* replay surface-create and cursor-set commands */
2346 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2347 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2348 if (d->guest_surfaces.cmds[in] == 0) {
2351 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2356 if (d->guest_cursor) {
2357 cmds[out].cmd.data = d->guest_cursor;
2364 if (d->guest_monitors_config) {
2371 qxl_set_mode(d, d->shadow_rom.mode, 1);
2383 return qxl->guest_monitors_config != 0;
2388 .name = "qxl-memslot",
2400 .name = "qxl-surface",
2418 .name = "qxl/monitors-config",
2469 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2470 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2471 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2477 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2484 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); local
2486 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2487 k->device_id = QXL_DEVICE_ID_STABLE;
2488 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2490 dc->vmsd = &qxl_vmstate;
2509 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); local
2511 k->realize = qxl_realize_primary;
2512 k->romfile = "vgabios-qxl.bin";
2513 k->class_id = PCI_CLASS_DISPLAY_VGA;
2514 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2515 dc->hotpluggable = false;
2519 .name = "qxl-vga",
2523 module_obj("qxl-vga");
2529 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); local
2531 k->realize = qxl_realize_secondary;
2532 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2533 dc->desc = "Spice QXL GPU (secondary)";
2552 module_dep("ui-spice-core");