Lines Matching +full:0 +full:x40a0
40 #define EXYNOS4210_FIMD_DEBUG 0
41 #define EXYNOS4210_FIMD_MODE_TRACE 0
43 #if EXYNOS4210_FIMD_DEBUG == 0
44 #define DPRINT_L1(fmt, args...) do { } while (0)
45 #define DPRINT_L2(fmt, args...) do { } while (0)
48 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
49 #define DPRINT_L2(fmt, args...) do { } while (0)
52 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
54 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
57 #if EXYNOS4210_FIMD_MODE_TRACE == 0
58 #define DPRINT_TRACE(fmt, args...) do { } while (0)
61 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
65 #define FIMD_REGS_SIZE 0x4114
68 #define FIMD_VIDCON0 0x0000
69 #define FIMD_VIDCON1 0x0004
70 #define FIMD_VIDCON2 0x0008
71 #define FIMD_VIDCON3 0x000C
72 #define FIMD_VIDCON0_ENVID_F (1 << 0)
74 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
75 #define FIMD_VIDCON1_ROMASK 0x07FFE000
78 #define FIMD_VIDTCON_START 0x10
79 #define FIMD_VIDTCON_END 0x1C
80 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF
81 #define FIMD_VIDTCON2_HOR_SHIFT 0
85 #define FIMD_WINCON_START 0x0020
86 #define FIMD_WINCON_END 0x0030
87 #define FIMD_WINCON_ROMASK 0x82200000
88 #define FIMD_WINCON_ENWIN (1 << 0)
92 #define FIMD_WINCON_SWAP 0x078000
94 #define FIMD_WINCON_SWAP_WORD 0x1
95 #define FIMD_WINCON_SWAP_HWORD 0x2
96 #define FIMD_WINCON_SWAP_BYTE 0x4
97 #define FIMD_WINCON_SWAP_BITS 0x8
101 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
102 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
103 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31))
105 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
106 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
107 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
109 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
111 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
113 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
116 #define FIMD_SHADOWCON 0x0034
119 #define FIMD_WINCHMAP 0x003C
122 #define FIMD_VIDOSD_START 0x0040
123 #define FIMD_VIDOSD_END 0x0088
124 #define FIMD_VIDOSD_COORD_MASK 0x07FF
126 #define FIMD_VIDOSD_VER_SHIFT 0
127 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
129 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
132 #define FIMD_VIDWADD0_START 0x00A0
133 #define FIMD_VIDWADD0_END 0x00C4
134 #define FIMD_VIDWADD0_END 0x00C4
135 #define FIMD_VIDWADD1_START 0x00D0
136 #define FIMD_VIDWADD1_END 0x00F4
137 #define FIMD_VIDWADD2_START 0x0100
138 #define FIMD_VIDWADD2_END 0x0110
139 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
140 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF
142 #define FIMD_VIDW0ADD0_B2 0x20A0
143 #define FIMD_VIDW4ADD0_B2 0x20C0
146 #define FIMD_VIDINTCON0 0x130
147 #define FIMD_VIDINTCON1 0x134
150 #define FIMD_WKEYCON_START 0x140
151 #define FIMD_WKEYCON_END 0x15C
152 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
158 #define FIMD_WKEYALPHA_START 0x160
159 #define FIMD_WKEYALPHA_END 0x16C
162 #define FIMD_DITHMODE 0x170
165 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
166 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
167 #define FIMD_VIDWALPHA_START 0x21C
168 #define FIMD_VIDWALPHA_END 0x240
171 #define FIMD_WINMAP_START 0x180
172 #define FIMD_WINMAP_END 0x190
174 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
177 #define FIMD_WPALCON_HIGH 0x019C
178 #define FIMD_WPALCON_LOW 0x01A0
180 #define FIMD_WPAL_W0PAL_L 0x07
181 #define FIMD_WPAL_W0PAL_L_SHT 0
182 #define FIMD_WPAL_W1PAL_L 0x07
184 #define FIMD_WPAL_W2PAL_L 0x01
186 #define FIMD_WPAL_W2PAL_H 0x06
188 #define FIMD_WPAL_W3PAL_L 0x01
190 #define FIMD_WPAL_W3PAL_H 0x06
192 #define FIMD_WPAL_W4PAL_L 0x01
194 #define FIMD_WPAL_W4PAL_H 0x06
198 #define FIMD_TRIGCON 0x01A4
199 #define FIMD_TRIGCON_ROMASK 0x00000004
202 #define FIMD_I80IFCON_START 0x01B0
203 #define FIMD_I80IFCON_END 0x01BC
205 #define FIMD_COLORGAINCON 0x01C0
207 #define FIMD_LDI_CMDCON0 0x01D0
208 #define FIMD_LDI_CMDCON1 0x01D4
210 #define FIMD_SIFCCON0 0x01E0
211 #define FIMD_SIFCCON2 0x01E8
214 #define FIMD_HUECOEFCR_START 0x01EC
215 #define FIMD_HUECOEFCR_END 0x01F4
216 #define FIMD_HUECOEFCB_START 0x01FC
217 #define FIMD_HUECOEFCB_END 0x0208
218 #define FIMD_HUEOFFSET 0x020C
221 #define FIMD_VIDINT_INTFIFOPEND (1 << 0)
224 #define FIMD_VIDINT_INTEN (1 << 0)
230 #define FIMD_BLENDEQ_START 0x0244
231 #define FIMD_BLENDEQ_END 0x0250
232 #define FIMD_BLENDCON 0x0260
233 #define FIMD_ALPHA_8BIT (1 << 0)
234 #define FIMD_BLENDEQ_COEF_MASK 0xF
237 #define FIMD_WRTQOSCON_START 0x0264
238 #define FIMD_WRTQOSCON_END 0x0274
241 #define FIMD_I80IFCMD_START 0x0280
242 #define FIMD_I80IFCMD_END 0x02AC
245 #define FIMD_SHD_ADD0_START 0x40A0
246 #define FIMD_SHD_ADD0_END 0x40C0
247 #define FIMD_SHD_ADD1_START 0x40D0
248 #define FIMD_SHD_ADD1_END 0x40F0
249 #define FIMD_SHD_ADD2_START 0x4100
250 #define FIMD_SHD_ADD2_END 0x4110
253 #define FIMD_PAL_MEM_START 0x2400
254 #define FIMD_PAL_MEM_END 0x37FC
255 /* Palette memory aliases for windows 0 and 1 */
256 #define FIMD_PALMEM_AL_START 0x0400
257 #define FIMD_PALMEM_AL_END 0x0BFC
261 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
309 uint32_t vidcon[4]; /* Video main control registers 0-3 */
310 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
341 res = 0; in fimd_swap_data()
342 for (i = 0; i < 64; i++) { in fimd_swap_data()
355 x = ((x & 0x000000000000FFFFULL) << 48) | in fimd_swap_data()
356 ((x & 0x00000000FFFF0000ULL) << 16) | in fimd_swap_data()
357 ((x & 0x0000FFFF00000000ULL) >> 16) | in fimd_swap_data()
358 ((x & 0xFFFF000000000000ULL) >> 48); in fimd_swap_data()
362 x = ((x & 0x00000000FFFFFFFFULL) << 32) | in fimd_swap_data()
363 ((x & 0xFFFFFFFF00000000ULL) >> 32); in fimd_swap_data()
373 * example, if blue component has only two possible values 0 and 1 it will be
374 * extended to 0 and 0xFF */
389 p->a = (pixel & 0x1); \
411 p->a = 0x0; \
442 0x0, 0x55, 0xAA, 0xFF
446 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
451 p->b = pixel_lutable_2b[(pixel & 0x3)]; in pixel_a232_to_rgb()
453 p->g = pixel_lutable_3b[(pixel & 0x7)]; in pixel_a232_to_rgb()
455 p->r = pixel_lutable_2b[(pixel & 0x3)]; in pixel_a232_to_rgb()
457 p->a = (pixel & 0x1); in pixel_a232_to_rgb()
465 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); in pixel_1555_to_rgb()
467 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); in pixel_1555_to_rgb()
469 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3); in pixel_1555_to_rgb()
470 p->a = 0x0; in pixel_1555_to_rgb()
489 p->a = (*(uint32_t *)s) & 0x00FFFFFF; in get_pixel_ifb()
494 [0] = pixel_565_to_rgb,
511 case 0: in exynos4210_fimd_palette_format()
524 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) | in exynos4210_fimd_palette_format()
528 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) | in exynos4210_fimd_palette_format()
532 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) | in exynos4210_fimd_palette_format()
537 ret = 0; in exynos4210_fimd_palette_format()
544 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
545 (0xFF0000 - ((x) & 0xFF0000)))
546 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
547 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
550 * Each byte with values 0-255 is considered as a number with possible values
551 * in a range [0 - 1] */
557 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp; in fimd_mult_each_byte()
558 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? in fimd_mult_each_byte()
559 0xFF00 : tmp << 8; in fimd_mult_each_byte()
560 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? in fimd_mult_each_byte()
561 0xFF0000 : tmp << 16; in fimd_mult_each_byte()
566 * Byte values 0-255 are mapped to a range [0 .. 1] */
573 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF)) in fimd_mult_and_sum_each_byte()
574 > 0xFF) ? 0xFF : tmp; in fimd_mult_and_sum_each_byte()
575 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) * in fimd_mult_and_sum_each_byte()
576 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8; in fimd_mult_and_sum_each_byte()
577 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) + in fimd_mult_and_sum_each_byte()
578 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ? in fimd_mult_and_sum_each_byte()
579 0xFF0000 : tmp << 16; in fimd_mult_and_sum_each_byte()
606 return fimd_mult_each_byte(pix_a, w->alpha_val[0]); in fimd_get_alpha_mult()
612 EXTEND_UPPER_HALFBYTE(w->alpha_val[0])); in fimd_get_alpha_mult_ext()
627 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0]; in fimd_get_alpha_sel()
633 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]); in fimd_get_alpha_sel_ext()
679 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) | in exynos4210_fimd_blend_pixel()
680 (p_bg.b & 0xFF); in exynos4210_fimd_blend_pixel()
681 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) | in exynos4210_fimd_blend_pixel()
682 (p_fg.b & 0xFF); in exynos4210_fimd_blend_pixel()
687 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4}; in exynos4210_fimd_blend_pixel()
691 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) { in exynos4210_fimd_blend_pixel()
693 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY; in exynos4210_fimd_blend_pixel()
695 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) && in exynos4210_fimd_blend_pixel()
696 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { in exynos4210_fimd_blend_pixel()
698 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { in exynos4210_fimd_blend_pixel()
703 alpha_fg = 0; in exynos4210_fimd_blend_pixel()
704 blend_param[A_COEF] = 0xFFFFFF; in exynos4210_fimd_blend_pixel()
705 blend_param[B_COEF] = 0x0; in exynos4210_fimd_blend_pixel()
708 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 && in exynos4210_fimd_blend_pixel()
709 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) { in exynos4210_fimd_blend_pixel()
711 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) { in exynos4210_fimd_blend_pixel()
716 alpha_fg = 0; in exynos4210_fimd_blend_pixel()
717 blend_param[A_COEF] = 0x0; in exynos4210_fimd_blend_pixel()
718 blend_param[B_COEF] = 0xFFFFFF; in exynos4210_fimd_blend_pixel()
726 case 0: in exynos4210_fimd_blend_pixel()
727 blend_param[i] = 0; in exynos4210_fimd_blend_pixel()
730 blend_param[i] = 0xFFFFFF; in exynos4210_fimd_blend_pixel()
745 blend_param[i] = w->alpha_val[0]; in exynos4210_fimd_blend_pixel()
767 ret->b = fg_color & 0xFF; in exynos4210_fimd_blend_pixel()
769 ret->g = fg_color & 0xFF; in exynos4210_fimd_blend_pixel()
771 ret->r = fg_color & 0xFF; in exynos4210_fimd_blend_pixel()
796 for (i = (64 / (N) - 1); i >= 0; i--) { \
807 } while (width > 0); \
825 for (i = (64 / (N) - 1); i >= 0; i--) { \
835 } while (width > 0); \
892 *(uint8_t *)d++ = (pixel >> 0) & 0xFF; in put_to_qemufb_pixel24()
893 *(uint8_t *)d++ = (pixel >> 8) & 0xFF; in put_to_qemufb_pixel24()
894 *(uint8_t *)d++ = (pixel >> 16) & 0xFF; in put_to_qemufb_pixel24()
953 case 0: in exynos4210_fimd_update_win_bppmode()
1034 #if EXYNOS4210_FIMD_MODE_TRACE > 0
1038 case 0: in exynos4210_fimd_get_bppmode()
1081 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n", in exynos4210_fimd_trace_bppmode()
1082 win_num, w->winmap & 0xFFFFFF); in exynos4210_fimd_trace_bppmode()
1086 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) { in exynos4210_fimd_trace_bppmode()
1090 exynos4210_fimd_get_bppmode((val >> 2) & 0xF)); in exynos4210_fimd_trace_bppmode()
1104 return 0; in fimd_get_buffer_id()
1111 return 0; in fimd_get_buffer_id()
1134 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0); in fimd_update_memory_section()
1136 w->fb_len = 0; in fimd_update_memory_section()
1155 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n", in fimd_update_memory_section()
1178 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0); in fimd_update_memory_section()
1190 w->fb_len = 0; in fimd_update_memory_section()
1198 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_enable()
1208 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4); in unpack_upper_4()
1213 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) | in pack_upper_4()
1214 ((x & 0xF0) >> 4)) & 0xFFF; in pack_upper_4()
1219 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) { in exynos4210_fimd_update_irq()
1220 qemu_irq_lower(s->irq[0]); in exynos4210_fimd_update_irq()
1225 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) && in exynos4210_fimd_update_irq()
1227 qemu_irq_raise(s->irq[0]); in exynos4210_fimd_update_irq()
1229 qemu_irq_lower(s->irq[0]); in exynos4210_fimd_update_irq()
1231 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) && in exynos4210_fimd_update_irq()
1237 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) && in exynos4210_fimd_update_irq()
1261 memset(s->ifb, 0, width * height * RGBA_SIZE + 1); in exynos4210_update_resolution()
1282 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { in exynos4210_fimd_update()
1290 for (i = 0; i < NUM_OF_WINDOWS; i++) { in exynos4210_fimd_update()
1302 for (line = 0; line < scrn_height; line++) { in exynos4210_fimd_update()
1324 if (first_line >= 0) { in exynos4210_fimd_update()
1340 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) { in exynos4210_fimd_update()
1352 /* Set all display controller registers to 0 */ in exynos4210_fimd_reset()
1353 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon); in exynos4210_fimd_reset()
1354 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_reset()
1355 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow)); in exynos4210_fimd_reset()
1356 s->window[w].blendeq = 0xC2; in exynos4210_fimd_reset()
1358 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); in exynos4210_fimd_reset()
1368 s->winchmap = 0x7D517D51; in exynos4210_fimd_reset()
1369 s->colorgaincon = 0x10040100; in exynos4210_fimd_reset()
1370 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100; in exynos4210_fimd_reset()
1371 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100; in exynos4210_fimd_reset()
1372 s->hueoffset = 0x01800080; in exynos4210_fimd_reset()
1382 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset, in exynos4210_fimd_write()
1390 if ((val & FIMD_VIDCON0_ENVID) == 0) { in exynos4210_fimd_write()
1394 s->vidcon[0] = val; in exynos4210_fimd_write()
1415 if (w == 0) { in exynos4210_fimd_write()
1416 /* Window 0 wincon ALPHA_MUL bit must always be 0 */ in exynos4210_fimd_write()
1447 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_write()
1459 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; in exynos4210_fimd_write()
1461 case 0: in exynos4210_fimd_write()
1482 if (w == 0) { in exynos4210_fimd_write()
1485 s->window[w].alpha_val[0] = in exynos4210_fimd_write()
1488 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER); in exynos4210_fimd_write()
1497 "FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n", in exynos4210_fimd_write()
1533 s->vidintcon[0] = val; in exynos4210_fimd_write()
1558 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF); in exynos4210_fimd_write()
1566 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_write()
1605 if (w == 0) { in exynos4210_fimd_write()
1619 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_write()
1631 if (offset & 0x0004) { in exynos4210_fimd_write()
1633 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", in exynos4210_fimd_write()
1647 if (offset & 0x0004) { in exynos4210_fimd_write()
1649 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", in exynos4210_fimd_write()
1656 if (offset & 0x0004) { in exynos4210_fimd_write()
1658 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", in exynos4210_fimd_write()
1669 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; in exynos4210_fimd_write()
1673 /* Palette memory aliases for windows 0 and 1 */ in exynos4210_fimd_write()
1675 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; in exynos4210_fimd_write()
1680 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset); in exynos4210_fimd_write()
1690 uint32_t ret = 0; in exynos4210_fimd_read()
1692 DPRINT_L2("read offset 0x%08x\n", offset); in exynos4210_fimd_read()
1707 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2; in exynos4210_fimd_read()
1709 case 0: in exynos4210_fimd_read()
1720 if (w == 0) { in exynos4210_fimd_read()
1723 ret = (pack_upper_4(s->window[w].alpha_val[0]) << in exynos4210_fimd_read()
1731 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", in exynos4210_fimd_read()
1733 return 0xBAADBAAD; in exynos4210_fimd_read()
1789 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER); in exynos4210_fimd_read()
1799 if (offset & 0x0004) { in exynos4210_fimd_read()
1804 if (offset & 0x0004) { in exynos4210_fimd_read()
1809 if (offset & 0x0004) { in exynos4210_fimd_read()
1817 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF; in exynos4210_fimd_read()
1820 /* Palette aliases for win 0,1 */ in exynos4210_fimd_read()
1822 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF; in exynos4210_fimd_read()
1827 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset); in exynos4210_fimd_read()
1828 return 0xBAADBAAD; in exynos4210_fimd_read()
1851 for (w = 0; w < NUM_OF_WINDOWS; w++) { in exynos4210_fimd_load()
1860 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) == in exynos4210_fimd_load()
1862 return 0; in exynos4210_fimd_load()
1941 sysbus_init_irq(dev, &s->irq[0]); in exynos4210_fimd_init()
1959 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s); in exynos4210_fimd_realize()