5  * Copyright (c) 2013 Mark Cave-Ayland
29 #include "qemu/error-report.h"
35 #include "hw/qdev-properties.h"
78     MemoryRegion rom;  member
91     DisplaySurface *surface = qemu_console_surface(s->con);  in cg3_update_display()
103     width = s->width;  in cg3_update_display()
104     height = s->height;  in cg3_update_display()
106     y_start = -1;  in cg3_update_display()
107     pix = memory_region_get_ram_ptr(&s->vram_mem);  in cg3_update_display()
110     if (!s->full_update) {  in cg3_update_display()
111         snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0,  in cg3_update_display()
112                                               memory_region_size(&s->vram_mem),  in cg3_update_display()
121         if (s->full_update) {  in cg3_update_display()
124             update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page,  in cg3_update_display()
135                 dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];  in cg3_update_display()
140                 dpy_gfx_update(s->con, 0, y_start, width, y - y_start);  in cg3_update_display()
141                 y_start = -1;  in cg3_update_display()
147     s->full_update = 0;  in cg3_update_display()
149         dpy_gfx_update(s->con, 0, y_start, width, y - y_start);  in cg3_update_display()
152     if (s->regs[0] & CG3_CR_ENABLE_INTS) {  in cg3_update_display()
153         s->regs[1] |= CG3_SR_PENDING_INT;  in cg3_update_display()
154         qemu_irq_raise(s->irq);  in cg3_update_display()
163     memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);  in cg3_invalidate_display()
166 static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)  in cg3_reg_read()  argument
171     switch (addr) {  in cg3_reg_read()
177         val = s->regs[0];  in cg3_reg_read()
181         val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;  in cg3_reg_read()
183     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:  in cg3_reg_read()
184         val = s->regs[addr - 0x10];  in cg3_reg_read()
190                   addr, size);  in cg3_reg_read()
194     trace_cg3_read(addr, val, size);  in cg3_reg_read()
199 static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,  in cg3_reg_write()  argument
206     trace_cg3_write(addr, val, size);  in cg3_reg_write()
207     switch (addr) {  in cg3_reg_write()
209         s->dac_index = val;  in cg3_reg_write()
210         s->dac_state = 0;  in cg3_reg_write()
221             switch (s->dac_state) {  in cg3_reg_write()
223                 s->r[s->dac_index] = regval;  in cg3_reg_write()
224                 s->dac_state++;  in cg3_reg_write()
227                 s->g[s->dac_index] = regval;  in cg3_reg_write()
228                 s->dac_state++;  in cg3_reg_write()
231                 s->b[s->dac_index] = regval;  in cg3_reg_write()
233                 s->dac_index = (s->dac_index + 1) & 0xff;  in cg3_reg_write()
236                 s->dac_state = 0;  in cg3_reg_write()
241         s->full_update = 1;  in cg3_reg_write()
244         s->regs[0] = val;  in cg3_reg_write()
247         if (s->regs[1] & CG3_SR_PENDING_INT) {  in cg3_reg_write()
249             s->regs[1] &= ~CG3_SR_PENDING_INT;  in cg3_reg_write()
250             qemu_irq_lower(s->irq);  in cg3_reg_write()
253     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:  in cg3_reg_write()
254         s->regs[addr - 0x10] = val;  in cg3_reg_write()
260                   addr, size, val);  in cg3_reg_write()
285     memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom",  in cg3_initfn()
287     sysbus_init_mmio(sbd, &s->rom);  in cg3_initfn()
289     memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",  in cg3_initfn()
291     sysbus_init_mmio(sbd, &s->reg);  in cg3_initfn()
301     /* FCode ROM */  in cg3_realizefn()
302     vmstate_register_ram_global(&s->rom);  in cg3_realizefn()
305         ret = load_image_mr(fcode_filename, &s->rom);  in cg3_realizefn()
312     memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,  in cg3_realizefn()
314     memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);  in cg3_realizefn()
315     sysbus_init_mmio(sbd, &s->vram_mem);  in cg3_realizefn()
317     sysbus_init_irq(sbd, &s->irq);  in cg3_realizefn()
319     s->con = graphic_console_init(dev, 0, &cg3_ops, s);  in cg3_realizefn()
320     qemu_console_resize(s->con, s->width, s->height);  in cg3_realizefn()
355     memset(s->r, 0, 256);  in cg3_reset()
356     memset(s->g, 0, 256);  in cg3_reset()
357     memset(s->b, 0, 256);  in cg3_reset()
359     s->dac_state = 0;  in cg3_reset()
360     s->full_update = 1;  in cg3_reset()
361     qemu_irq_lower(s->irq);  in cg3_reset()
365     DEFINE_PROP_UINT32("vram-size",    CG3State, vram_size, -1),
366     DEFINE_PROP_UINT16("width",        CG3State, width,     -1),
367     DEFINE_PROP_UINT16("height",       CG3State, height,    -1),
368     DEFINE_PROP_UINT16("depth",        CG3State, depth,     -1),
375     dc->realize = cg3_realizefn;  in cg3_class_init()
377     dc->vmsd = &vmstate_cg3;  in cg3_class_init()