Lines Matching full:s
106 static void serial_xmit(SerialState *s);
108 static inline void recv_fifo_put(SerialState *s, uint8_t chr) in recv_fifo_put() argument
111 if (!fifo8_is_full(&s->recv_fifo)) { in recv_fifo_put()
112 fifo8_push(&s->recv_fifo, chr); in recv_fifo_put()
114 s->lsr |= UART_LSR_OE; in recv_fifo_put()
118 static void serial_update_irq(SerialState *s) in serial_update_irq() argument
122 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { in serial_update_irq()
124 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { in serial_update_irq()
125 /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, in serial_update_irq()
129 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && in serial_update_irq()
130 (!(s->fcr & UART_FCR_FE) || in serial_update_irq()
131 s->recv_fifo.num >= s->recv_fifo_itl)) { in serial_update_irq()
133 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { in serial_update_irq()
135 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { in serial_update_irq()
139 s->iir = tmp_iir | (s->iir & 0xF0); in serial_update_irq()
142 qemu_irq_raise(s->irq); in serial_update_irq()
144 qemu_irq_lower(s->irq); in serial_update_irq()
148 static void serial_update_parameters(SerialState *s) in serial_update_parameters() argument
156 if (s->lcr & 0x08) { in serial_update_parameters()
159 if (s->lcr & 0x10) in serial_update_parameters()
166 if (s->lcr & 0x04) { in serial_update_parameters()
172 data_bits = (s->lcr & 0x03) + 5; in serial_update_parameters()
175 speed = (s->divider == 0) ? 3500 : (float) s->baudbase / s->divider; in serial_update_parameters()
180 s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; in serial_update_parameters()
181 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); in serial_update_parameters()
185 static void serial_update_msl(SerialState *s) in serial_update_msl() argument
190 timer_del(s->modem_status_poll); in serial_update_msl()
192 if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, in serial_update_msl()
194 s->poll_msl = -1; in serial_update_msl()
198 omsr = s->msr; in serial_update_msl()
200 s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; in serial_update_msl()
201 s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; in serial_update_msl()
202 s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; in serial_update_msl()
203 s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; in serial_update_msl()
205 if (s->msr != omsr) { in serial_update_msl()
207 s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); in serial_update_msl()
209 if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) in serial_update_msl()
210 s->msr &= ~UART_MSR_TERI; in serial_update_msl()
211 serial_update_irq(s); in serial_update_msl()
217 if (s->poll_msl) { in serial_update_msl()
218 timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + in serial_update_msl()
226 SerialState *s = opaque; in serial_watch_cb() local
227 s->watch_tag = 0; in serial_watch_cb()
228 serial_xmit(s); in serial_watch_cb()
232 static void serial_xmit(SerialState *s) in serial_xmit() argument
235 assert(!(s->lsr & UART_LSR_TEMT)); in serial_xmit()
236 if (s->tsr_retry == 0) { in serial_xmit()
237 assert(!(s->lsr & UART_LSR_THRE)); in serial_xmit()
239 if (s->fcr & UART_FCR_FE) { in serial_xmit()
240 assert(!fifo8_is_empty(&s->xmit_fifo)); in serial_xmit()
241 s->tsr = fifo8_pop(&s->xmit_fifo); in serial_xmit()
242 if (!s->xmit_fifo.num) { in serial_xmit()
243 s->lsr |= UART_LSR_THRE; in serial_xmit()
246 s->tsr = s->thr; in serial_xmit()
247 s->lsr |= UART_LSR_THRE; in serial_xmit()
249 if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { in serial_xmit()
250 s->thr_ipending = 1; in serial_xmit()
251 serial_update_irq(s); in serial_xmit()
255 if (s->mcr & UART_MCR_LOOP) { in serial_xmit()
257 serial_receive1(s, &s->tsr, 1); in serial_xmit()
259 int rc = qemu_chr_fe_write(&s->chr, &s->tsr, 1); in serial_xmit()
263 s->tsr_retry < MAX_XMIT_RETRY) { in serial_xmit()
264 assert(s->watch_tag == 0); in serial_xmit()
265 s->watch_tag = in serial_xmit()
266 qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in serial_xmit()
267 serial_watch_cb, s); in serial_xmit()
268 if (s->watch_tag > 0) { in serial_xmit()
269 s->tsr_retry++; in serial_xmit()
274 s->tsr_retry = 0; in serial_xmit()
278 } while (!(s->lsr & UART_LSR_THRE)); in serial_xmit()
280 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in serial_xmit()
281 s->lsr |= UART_LSR_TEMT; in serial_xmit()
287 static void serial_write_fcr(SerialState *s, uint8_t val) in serial_write_fcr() argument
290 s->fcr = val; in serial_write_fcr()
293 s->iir |= UART_IIR_FE; in serial_write_fcr()
297 s->recv_fifo_itl = 1; in serial_write_fcr()
300 s->recv_fifo_itl = 4; in serial_write_fcr()
303 s->recv_fifo_itl = 8; in serial_write_fcr()
306 s->recv_fifo_itl = 14; in serial_write_fcr()
310 s->iir &= ~UART_IIR_FE; in serial_write_fcr()
314 static void serial_update_tiocm(SerialState *s) in serial_update_tiocm() argument
318 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags); in serial_update_tiocm()
322 if (s->mcr & UART_MCR_RTS) { in serial_update_tiocm()
325 if (s->mcr & UART_MCR_DTR) { in serial_update_tiocm()
329 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags); in serial_update_tiocm()
335 SerialState *s = opaque; in serial_ioport_write() local
342 if (s->lcr & UART_LCR_DLAB) { in serial_ioport_write()
343 s->divider = deposit32(s->divider, 8 * addr, 8, val); in serial_ioport_write()
344 serial_update_parameters(s); in serial_ioport_write()
346 s->thr = (uint8_t) val; in serial_ioport_write()
347 if(s->fcr & UART_FCR_FE) { in serial_ioport_write()
349 if (fifo8_is_full(&s->xmit_fifo)) { in serial_ioport_write()
350 fifo8_pop(&s->xmit_fifo); in serial_ioport_write()
352 fifo8_push(&s->xmit_fifo, s->thr); in serial_ioport_write()
354 s->thr_ipending = 0; in serial_ioport_write()
355 s->lsr &= ~UART_LSR_THRE; in serial_ioport_write()
356 s->lsr &= ~UART_LSR_TEMT; in serial_ioport_write()
357 serial_update_irq(s); in serial_ioport_write()
358 if (s->tsr_retry == 0) { in serial_ioport_write()
359 serial_xmit(s); in serial_ioport_write()
364 if (s->lcr & UART_LCR_DLAB) { in serial_ioport_write()
365 s->divider = deposit32(s->divider, 8 * addr, 8, val); in serial_ioport_write()
366 serial_update_parameters(s); in serial_ioport_write()
368 uint8_t changed = (s->ier ^ val) & 0x0f; in serial_ioport_write()
369 s->ier = val & 0x0f; in serial_ioport_write()
373 if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { in serial_ioport_write()
374 if (s->ier & UART_IER_MSI) { in serial_ioport_write()
375 s->poll_msl = 1; in serial_ioport_write()
376 serial_update_msl(s); in serial_ioport_write()
378 timer_del(s->modem_status_poll); in serial_ioport_write()
379 s->poll_msl = 0; in serial_ioport_write()
395 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { in serial_ioport_write()
396 s->thr_ipending = 1; in serial_ioport_write()
398 s->thr_ipending = 0; in serial_ioport_write()
403 serial_update_irq(s); in serial_ioport_write()
409 if ((val ^ s->fcr) & UART_FCR_FE) { in serial_ioport_write()
416 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); in serial_ioport_write()
417 timer_del(s->fifo_timeout_timer); in serial_ioport_write()
418 s->timeout_ipending = 0; in serial_ioport_write()
419 fifo8_reset(&s->recv_fifo); in serial_ioport_write()
423 s->lsr |= UART_LSR_THRE; in serial_ioport_write()
424 s->thr_ipending = 1; in serial_ioport_write()
425 fifo8_reset(&s->xmit_fifo); in serial_ioport_write()
428 serial_write_fcr(s, val & 0xC9); in serial_ioport_write()
429 serial_update_irq(s); in serial_ioport_write()
434 s->lcr = val; in serial_ioport_write()
435 serial_update_parameters(s); in serial_ioport_write()
437 if (break_enable != s->last_break_enable) { in serial_ioport_write()
438 s->last_break_enable = break_enable; in serial_ioport_write()
439 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, in serial_ioport_write()
446 int old_mcr = s->mcr; in serial_ioport_write()
447 s->mcr = val & 0x1f; in serial_ioport_write()
451 if (s->poll_msl >= 0 && old_mcr != s->mcr) { in serial_ioport_write()
452 serial_update_tiocm(s); in serial_ioport_write()
455 … timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); in serial_ioport_write()
464 s->scr = val; in serial_ioport_write()
471 SerialState *s = opaque; in serial_ioport_read() local
478 if (s->lcr & UART_LCR_DLAB) { in serial_ioport_read()
479 ret = extract16(s->divider, 8 * addr, 8); in serial_ioport_read()
481 if(s->fcr & UART_FCR_FE) { in serial_ioport_read()
482 ret = fifo8_is_empty(&s->recv_fifo) ? in serial_ioport_read()
483 0 : fifo8_pop(&s->recv_fifo); in serial_ioport_read()
484 if (s->recv_fifo.num == 0) { in serial_ioport_read()
485 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); in serial_ioport_read()
487 …timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4… in serial_ioport_read()
489 s->timeout_ipending = 0; in serial_ioport_read()
491 ret = s->rbr; in serial_ioport_read()
492 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); in serial_ioport_read()
494 serial_update_irq(s); in serial_ioport_read()
495 if (!(s->mcr & UART_MCR_LOOP)) { in serial_ioport_read()
497 qemu_chr_fe_accept_input(&s->chr); in serial_ioport_read()
502 if (s->lcr & UART_LCR_DLAB) { in serial_ioport_read()
503 ret = extract16(s->divider, 8 * addr, 8); in serial_ioport_read()
505 ret = s->ier; in serial_ioport_read()
509 ret = s->iir; in serial_ioport_read()
511 s->thr_ipending = 0; in serial_ioport_read()
512 serial_update_irq(s); in serial_ioport_read()
516 ret = s->lcr; in serial_ioport_read()
519 ret = s->mcr; in serial_ioport_read()
522 ret = s->lsr; in serial_ioport_read()
524 if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { in serial_ioport_read()
525 s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); in serial_ioport_read()
526 serial_update_irq(s); in serial_ioport_read()
530 if (s->mcr & UART_MCR_LOOP) { in serial_ioport_read()
533 ret = (s->mcr & 0x0c) << 4; in serial_ioport_read()
534 ret |= (s->mcr & 0x02) << 3; in serial_ioport_read()
535 ret |= (s->mcr & 0x01) << 5; in serial_ioport_read()
537 if (s->poll_msl >= 0) in serial_ioport_read()
538 serial_update_msl(s); in serial_ioport_read()
539 ret = s->msr; in serial_ioport_read()
541 if (s->msr & UART_MSR_ANY_DELTA) { in serial_ioport_read()
542 s->msr &= 0xF0; in serial_ioport_read()
543 serial_update_irq(s); in serial_ioport_read()
548 ret = s->scr; in serial_ioport_read()
555 static int serial_can_receive(SerialState *s) in serial_can_receive() argument
557 if(s->fcr & UART_FCR_FE) { in serial_can_receive()
558 if (s->recv_fifo.num < UART_FIFO_LENGTH) { in serial_can_receive()
566 return (s->recv_fifo.num <= s->recv_fifo_itl) ? in serial_can_receive()
567 s->recv_fifo_itl - s->recv_fifo.num : 1; in serial_can_receive()
572 return !(s->lsr & UART_LSR_DR); in serial_can_receive()
576 static void serial_receive_break(SerialState *s) in serial_receive_break() argument
578 s->rbr = 0; in serial_receive_break()
580 recv_fifo_put(s, '\0'); in serial_receive_break()
581 s->lsr |= UART_LSR_BI | UART_LSR_DR; in serial_receive_break()
582 serial_update_irq(s); in serial_receive_break()
585 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
587 SerialState *s = opaque; in fifo_timeout_int() local
588 if (s->recv_fifo.num) { in fifo_timeout_int()
589 s->timeout_ipending = 1; in fifo_timeout_int()
590 serial_update_irq(s); in fifo_timeout_int()
596 SerialState *s = opaque; in serial_can_receive1() local
597 return serial_can_receive(s); in serial_can_receive1()
602 SerialState *s = opaque; in serial_receive1() local
604 if (s->wakeup) { in serial_receive1()
607 if(s->fcr & UART_FCR_FE) { in serial_receive1()
610 recv_fifo_put(s, buf[i]); in serial_receive1()
612 s->lsr |= UART_LSR_DR; in serial_receive1()
614 …timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4… in serial_receive1()
616 if (s->lsr & UART_LSR_DR) in serial_receive1()
617 s->lsr |= UART_LSR_OE; in serial_receive1()
618 s->rbr = buf[0]; in serial_receive1()
619 s->lsr |= UART_LSR_DR; in serial_receive1()
621 serial_update_irq(s); in serial_receive1()
626 SerialState *s = opaque; in serial_event() local
628 serial_receive_break(s); in serial_event()
633 SerialState *s = opaque; in serial_pre_save() local
634 s->fcr_vmstate = s->fcr; in serial_pre_save()
641 SerialState *s = opaque; in serial_pre_load() local
642 s->thr_ipending = -1; in serial_pre_load()
643 s->poll_msl = -1; in serial_pre_load()
649 SerialState *s = opaque; in serial_post_load() local
652 s->fcr_vmstate = 0; in serial_post_load()
654 if (s->thr_ipending == -1) { in serial_post_load()
655 s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); in serial_post_load()
658 if (s->tsr_retry > 0) { in serial_post_load()
660 if (s->lsr & UART_LSR_TEMT) { in serial_post_load()
662 "(tsr empty, tsr_retry=%d", s->tsr_retry); in serial_post_load()
666 if (s->tsr_retry > MAX_XMIT_RETRY) { in serial_post_load()
667 s->tsr_retry = MAX_XMIT_RETRY; in serial_post_load()
670 assert(s->watch_tag == 0); in serial_post_load()
671 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in serial_post_load()
672 serial_watch_cb, s); in serial_post_load()
675 if (!(s->lsr & UART_LSR_TEMT)) { in serial_post_load()
682 s->last_break_enable = (s->lcr >> 6) & 1; in serial_post_load()
684 serial_write_fcr(s, s->fcr_vmstate); in serial_post_load()
685 serial_update_parameters(s); in serial_post_load()
691 SerialState *s = opaque; in serial_thr_ipending_needed() local
693 if (s->ier & UART_IER_THRI) { in serial_thr_ipending_needed()
694 bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); in serial_thr_ipending_needed()
695 return s->thr_ipending != expected_value; in serial_thr_ipending_needed()
718 SerialState *s = (SerialState *)opaque; in serial_tsr_needed() local
719 return s->tsr_retry != 0; in serial_tsr_needed()
737 SerialState *s = (SerialState *)opaque; in serial_recv_fifo_needed() local
738 return !fifo8_is_empty(&s->recv_fifo); in serial_recv_fifo_needed()
755 SerialState *s = (SerialState *)opaque; in serial_xmit_fifo_needed() local
756 return !fifo8_is_empty(&s->xmit_fifo); in serial_xmit_fifo_needed()
772 SerialState *s = (SerialState *)opaque; in serial_fifo_timeout_timer_needed() local
773 return timer_pending(s->fifo_timeout_timer); in serial_fifo_timeout_timer_needed()
789 SerialState *s = (SerialState *)opaque; in serial_timeout_ipending_needed() local
790 return s->timeout_ipending != 0; in serial_timeout_ipending_needed()
806 SerialState *s = (SerialState *)opaque; in serial_poll_needed() local
807 return s->poll_msl >= 0; in serial_poll_needed()
856 SerialState *s = opaque; in serial_reset() local
858 if (s->watch_tag > 0) { in serial_reset()
859 g_source_remove(s->watch_tag); in serial_reset()
860 s->watch_tag = 0; in serial_reset()
863 s->rbr = 0; in serial_reset()
864 s->ier = 0; in serial_reset()
865 s->iir = UART_IIR_NO_INT; in serial_reset()
866 s->lcr = 0; in serial_reset()
867 s->lsr = UART_LSR_TEMT | UART_LSR_THRE; in serial_reset()
868 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; in serial_reset()
870 s->divider = 0x0C; in serial_reset()
871 s->mcr = UART_MCR_OUT2; in serial_reset()
872 s->scr = 0; in serial_reset()
873 s->tsr_retry = 0; in serial_reset()
874 s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10; in serial_reset()
875 s->poll_msl = 0; in serial_reset()
877 s->timeout_ipending = 0; in serial_reset()
878 timer_del(s->fifo_timeout_timer); in serial_reset()
879 timer_del(s->modem_status_poll); in serial_reset()
881 fifo8_reset(&s->recv_fifo); in serial_reset()
882 fifo8_reset(&s->xmit_fifo); in serial_reset()
884 s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in serial_reset()
886 s->thr_ipending = 0; in serial_reset()
887 s->last_break_enable = 0; in serial_reset()
888 qemu_irq_lower(s->irq); in serial_reset()
890 serial_update_msl(s); in serial_reset()
891 s->msr &= ~UART_MSR_ANY_DELTA; in serial_reset()
896 SerialState *s = opaque; in serial_be_change() local
898 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, in serial_be_change()
899 serial_event, serial_be_change, s, NULL, true); in serial_be_change()
901 serial_update_parameters(s); in serial_be_change()
903 qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, in serial_be_change()
904 &s->last_break_enable); in serial_be_change()
906 s->poll_msl = (s->ier & UART_IER_MSI) ? 1 : 0; in serial_be_change()
907 serial_update_msl(s); in serial_be_change()
909 if (s->poll_msl >= 0 && !(s->mcr & UART_MCR_LOOP)) { in serial_be_change()
910 serial_update_tiocm(s); in serial_be_change()
913 if (s->watch_tag > 0) { in serial_be_change()
914 g_source_remove(s->watch_tag); in serial_be_change()
915 s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, in serial_be_change()
916 serial_watch_cb, s); in serial_be_change()
924 SerialState *s = SERIAL(dev); in serial_realize() local
926 s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); in serial_realize()
928 s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); in serial_realize()
929 qemu_register_reset(serial_reset, s); in serial_realize()
931 qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, in serial_realize()
932 serial_event, serial_be_change, s, NULL, true); in serial_realize()
933 fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); in serial_realize()
934 fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); in serial_realize()
935 serial_reset(s); in serial_realize()
940 SerialState *s = SERIAL(dev); in serial_unrealize() local
942 qemu_chr_fe_deinit(&s->chr, false); in serial_unrealize()
944 timer_free(s->modem_status_poll); in serial_unrealize()
946 timer_free(s->fifo_timeout_timer); in serial_unrealize()
948 fifo8_destroy(&s->recv_fifo); in serial_unrealize()
949 fifo8_destroy(&s->xmit_fifo); in serial_unrealize()
951 qemu_unregister_reset(serial_reset, s); in serial_unrealize()