265             (s->rregs[R_STATUS] & STATUS_BRK)))) {  in escc_update_irq_chn()
314     s->rregs[R_STATUS] &= STATUS_DCD | STATUS_SYNC | STATUS_CTS | STATUS_BRK;  in escc_soft_reset_chn()
315     s->rregs[R_STATUS] |= STATUS_TXEMPTY | STATUS_TXUNDRN;  in escc_soft_reset_chn()
317         s->rregs[R_STATUS] |= STATUS_DCD | STATUS_SYNC | STATUS_CTS;  in escc_soft_reset_chn()
319     s->rregs[R_SPEC] &= SPEC_ALLSENT;  in escc_soft_reset_chn()
320     s->rregs[R_SPEC] |= SPEC_BITS8;  in escc_soft_reset_chn()
321     s->rregs[R_INTR] = 0;  in escc_soft_reset_chn()
322     s->rregs[R_MISC] &= MISC_2CLKMISS;  in escc_soft_reset_chn()
358             cs->rregs[j] = 0;  in escc_reset()
370         cs->rregs[R_STATUS] |= STATUS_TXEMPTY;  in escc_reset()
385         s->rregs[R_INTR] |= INTR_RXINTA;  in set_rxint()
387             s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;  in set_rxint()
389             s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;  in set_rxint()
392         s->otherchn->rregs[R_INTR] |= INTR_RXINTB;  in set_rxint()
394             s->rregs[R_IVEC] = IVEC_HIRXINTB;  in set_rxint()
396             s->rregs[R_IVEC] = IVEC_LORXINTB;  in set_rxint()
409                 s->rregs[R_INTR] |= INTR_TXINTA;  in set_txint()
412                 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;  in set_txint()
414                 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;  in set_txint()
417             s->rregs[R_IVEC] = IVEC_TXINTB;  in set_txint()
419                 s->otherchn->rregs[R_INTR] |= INTR_TXINTB;  in set_txint()
432             s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;  in clr_rxint()
434             s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;  in clr_rxint()
436         s->rregs[R_INTR] &= ~INTR_RXINTA;  in clr_rxint()
439             s->rregs[R_IVEC] = IVEC_HINOINT;  in clr_rxint()
441             s->rregs[R_IVEC] = IVEC_LONOINT;  in clr_rxint()
443         s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;  in clr_rxint()
457             s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;  in clr_txint()
459             s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;  in clr_txint()
461         s->rregs[R_INTR] &= ~INTR_TXINTA;  in clr_txint()
463         s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;  in clr_txint()
465             s->rregs[R_IVEC] = IVEC_HINOINT;  in clr_txint()
467             s->rregs[R_IVEC] = IVEC_LONOINT;  in clr_txint()
469         s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;  in clr_txint()
583                 s->rregs[R_STATUS] |= STATUS_SYNC;  in escc_mem_write()
604             s->rregs[R_SPEC] |= SPEC_ALLSENT;  in escc_mem_write()
614             s->rregs[s->reg] = val;  in escc_mem_write()
669         s->rregs[R_STATUS] |= STATUS_TXEMPTY; /* Tx buffer empty */  in escc_mem_write()
670         s->rregs[R_SPEC] |= SPEC_ALLSENT; /* All sent */  in escc_mem_write()
692         trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]);  in escc_mem_read()
693         ret = s->rregs[s->reg];  in escc_mem_read()
697         s->rregs[R_STATUS] &= ~STATUS_RXAV;  in escc_mem_read()
729         || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) {  in serial_can_receive()
741     s->rregs[R_STATUS] |= STATUS_RXAV;  in serial_receive_byte()
748     s->rregs[R_STATUS] |= STATUS_BRK;  in serial_receive_break()
780         VMSTATE_BUFFER(rregs, ESCCChannelState),