2  * GUSEMU32 - bus interface part
4  * Copyright (C) 2000-2007 Tibor "TS" Schütz
43     gusptr = state->gusdatapos;  in gus_read()
53         /* dma bit set in gus_dma_transferdata */  in gus_read()
73                 return GUSregb(IRQ_2xB);        /* control register select bit */  in gus_read()
76             /* case 1-5:                        */ /* general purpose emulation regs  */  in gus_read()
90         /* case 0x20D:                   */ /* SB2xD is write only -> 2xE writes to it*/  in gus_read()
95             GUS_irqrequest(state, state->gusirq, 1);  in gus_read()
99         /*set/clear fixed bits */  in gus_read()
119             if (state->gusdma >= 4)  in gus_read()
126                     GUS_irqclear(state, state->gusirq);  in gus_read()
135             /* 48h: samp freq - write only */  in gus_read()
165             /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */  in gus_read()
182             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);  in gus_read()
193     gusptr = state->gusdatapos;  in gus_write()
202         if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */  in gus_write()
206             GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
218 …      GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */  in gus_write()
229                 GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
241                 GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */  in gus_write()
245             /* case 1-4: general purpose emulation regs */  in gus_write()
246         case 5:                                    /* clear stat reg 2xF */  in gus_write()
249                 GUS_irqclear(state, state->gusirq);  in gus_write()
260             GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */  in gus_write()
262             GUS_irqrequest(state, state->gusirq, 1);  in gus_write()
279         if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */  in gus_write()
288                         GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */  in gus_write()
289                         GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */  in gus_write()
293                             GUS_irqclear(state, state->gusirq);  in gus_write()
294                         GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */  in gus_write()
305                         GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */  in gus_write()
306 …            GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */  in gus_write()
310                             GUS_irqclear(state, state->gusirq);  in gus_write()
311                         GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */  in gus_write()
386 …                GUSregb(TimerStatus2x8) &= 0xe7;    /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */  in gus_write()
388 …          GUSregb(TimerStatus2x8) &= 0xfe;    /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */  in gus_write()
390 …GUSregb(IRQStatReg2x6) &= 0xef;     /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared …  in gus_write()
400                             GUSregb(TimerStatus2x8) |= 4;       /* nonmaskable bit */  in gus_write()
410                             GUSregb(TimerStatus2x8) |= 2;       /* nonmaskable bit */  in gus_write()
414                     GUSregw(TimerIRQs)--;  in gus_write()
416                         GUSregw(BusyTimerIRQs)--;  in gus_write()
419                             GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));  in gus_write()
426                     GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */  in gus_write()
431                     GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */  in gus_write()
435                     GUS_irqclear(state, state->gusirq);  in gus_write()
464                     GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */  in gus_write()
465                     GUS_irqclear(state, state->gusirq);  in gus_write()
467                 /* IRQ enable bit checked elsewhere */  in gus_write()
468                 /* EnableDAC bit may be used by external callers */  in gus_write()
476             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);  in gus_write()
498  * GUSemu also uses this register to support byte-granular transfers for better compatibility
515     gusptr = state->gusdatapos;  in gus_dma_transferdata()
520         if (state->gusdma >= 4)  in gus_dma_transferdata()
521             offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */  in gus_dma_transferdata()
522         destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */  in gus_dma_transferdata()
525 …Start) += (uint16_t)  (count >> 4);                           /* ToDo: add 16bit GUS page limit? */  in gus_dma_transferdata()
526 …GUSregb(GUS50DMAHigh)   = (uint8_t) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GU…  in gus_dma_transferdata()
528     if (GUSregb(GUS41DMACtrl) & 0x02)   /* direction, 0 := sysram->gusram */  in gus_dma_transferdata()
537     for (; count > 0; count--)  in gus_dma_transferdata()
540             *(destaddr++) = *(srcaddr++);               /* 16 bit lobyte */  in gus_dma_transferdata()
542             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */  in gus_dma_transferdata()
543         if (state->gusdma >= 4)  in gus_dma_transferdata()
544             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */  in gus_dma_transferdata()
549         (GUSregb(GUS41DMACtrl)) &= 0xfe;        /* clear DMA request bit */  in gus_dma_transferdata()
553             GUS_irqrequest(state, state->gusirq, 1);  in gus_dma_transferdata()