28 #include "hw/adc/zynq-xadc.h"
31 #include "qemu/error-report.h"
36 #include "hw/qdev-clock.h"
41 #include "target/arm/cpu-qom.h"
44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
112     rom_add_blob_fixed("board-setup", board_setup_blob,  in zynq_write_board_setup()
125     object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort);  in gem_init()
144     dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");  in zynq_init_spi_flashes()
145     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);  in zynq_init_spi_flashes()
146     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);  in zynq_init_spi_flashes()
147     qdev_prop_set_uint8(dev, "num-busses", num_busses);  in zynq_init_spi_flashes()
200     m->boot_mode = mode;  in zynq_set_boot_mode()
212     unsigned int smp_cpus = machine->smp.cpus;  in zynq_init()
215     if (machine->ram_size > 2 * GiB) {  in zynq_init()
221         Object *cpuobj = object_new(machine->cpu_type);  in zynq_init()
225         object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,  in zynq_init()
230         zynq_machine->cpu[n] = ARM_CPU(cpuobj);  in zynq_init()
234     memory_region_add_subregion(address_space_mem, 0, machine->ram);  in zynq_init()
236     /* 256K of on-chip memory */  in zynq_init()
251     zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));  in zynq_init()
253                               OBJECT(zynq_machine->ps_clk));  in zynq_init()
254     object_unref(OBJECT(zynq_machine->ps_clk));  in zynq_init()
255     clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);  in zynq_init()
258     slcr = qdev_new("xilinx-zynq_slcr");  in zynq_init()
259     qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);  in zynq_init()
260     qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode);  in zynq_init()
265     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);  in zynq_init()
266     qdev_prop_set_uint32(dev, "num-irq", GIC_EXT_IRQS + GIC_INTERNAL);  in zynq_init()
274         DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);  in zynq_init()
285     n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0);  in zynq_init()
286     n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n);  in zynq_init()
287     n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n);  in zynq_init()
289     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]);  in zynq_init()
290     sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]);  in zynq_init()
299     sysbus_connect_irq(busdev, 0, pic[59 - GIC_INTERNAL]);  in zynq_init()
307     sysbus_connect_irq(busdev, 0, pic[82 - GIC_INTERNAL]);  in zynq_init()
310             pic[42-GIC_INTERNAL], pic[43-GIC_INTERNAL], pic[44-GIC_INTERNAL], NULL);  in zynq_init()
312             pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNAL], NULL);  in zynq_init()
314     gem_init(0xE000B000, pic[54 - GIC_INTERNAL]);  in zynq_init()
315     gem_init(0xE000C000, pic[77 - GIC_INTERNAL]);  in zynq_init()
325          * - SD Host Controller Specification Version 2.0 Part A2  in zynq_init()
326          * - SDIO Specification Version 2.0  in zynq_init()
327          * - MMC Specification Version 3.31  in zynq_init()
330         qdev_prop_set_uint8(dev, "sd-spec-version", 2);  in zynq_init()
334         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - GIC_INTERNAL]);  in zynq_init()
340         qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),  in zynq_init()
347     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-GIC_INTERNAL]);  in zynq_init()
367     sysbus_connect_irq(busdev, 0, pic[45-GIC_INTERNAL]); /* abort irq line */  in zynq_init()
369         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - GIC_INTERNAL]);  in zynq_init()
372     dev = qdev_new("xlnx.ps7-dev-cfg");  in zynq_init()
375     sysbus_connect_irq(busdev, 0, pic[40 - GIC_INTERNAL]);  in zynq_init()
379      * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and  in zynq_init()
380      * the zynq-7000.dtsi. Add placeholders for unimplemented devices.  in zynq_init()
389     /* Direct Memory Access Controller, PL330, Non-Secure Mode */  in zynq_init()
428     create_unimplemented_device("cortex-a9.pmu0", 0xF8891000, 4 * KiB);  in zynq_init()
429     create_unimplemented_device("cortex-a9.pmu1", 0xF8893000, 4 * KiB);  in zynq_init()
435     /* CoreSight PTM-A9, CPU */  in zynq_init()
436     create_unimplemented_device("cortex-a9.ptm0", 0xF889c000, 4 * KiB);  in zynq_init()
437     create_unimplemented_device("cortex-a9.ptm1", 0xF889d000, 4 * KiB);  in zynq_init()
442     /* AMBA Network Interconnect Advanced Quality of Service (QoS-301) */  in zynq_init()
447     zynq_binfo.ram_size = machine->ram_size;  in zynq_init()
453     arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);  in zynq_init()
459         ARM_CPU_TYPE_NAME("cortex-a9"),  in zynq_machine_class_init()
464     mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9";  in zynq_machine_class_init()
465     mc->init = zynq_init;  in zynq_machine_class_init()
466     mc->max_cpus = ZYNQ_MAX_CPUS;  in zynq_machine_class_init()
467     mc->ignore_memory_transaction_failures = true;  in zynq_machine_class_init()
468     mc->valid_cpu_types = valid_cpu_types;  in zynq_machine_class_init()
469     mc->default_ram_id = "zynq.ext_ram";  in zynq_machine_class_init()
470     prop = object_class_property_add_str(oc, "boot-mode", NULL,  in zynq_machine_class_init()
472     object_class_property_set_description(oc, "boot-mode",  in zynq_machine_class_init()