Lines Matching +full:1 +full:ms
152 * 256MB..1GB is reserved for possible future PCI support (ie where the
154 * 1GB and up is RAM (which may happily spill over into the
229 [VIRT_UART0] = 1,
235 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
236 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
237 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
238 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
241 static void create_randomness(MachineState *ms, const char *node) in create_randomness() argument
251 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr); in create_randomness()
252 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); in create_randomness()
271 MachineState *ms = MACHINE(vms); in create_fdt() local
272 int nb_numa_nodes = ms->numa_state->num_nodes; in create_fdt()
277 exit(1); in create_fdt()
280 ms->fdt = fdt; in create_fdt()
302 create_randomness(ms, "/chosen"); in create_fdt()
308 create_randomness(ms, "/secure-chosen"); in create_fdt()
328 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { in create_fdt()
337 matrix[idx + 1] = cpu_to_be32(j); in create_fdt()
339 cpu_to_be32(ms->numa_state->nodes[i].distance[j]); in create_fdt()
375 MachineState *ms = MACHINE(vms); in fdt_add_timer_nodes() local
384 (1 << MACHINE(vms)->smp.cpus) - 1); in fdt_add_timer_nodes()
387 qemu_fdt_add_subnode(ms->fdt, "/timer"); in fdt_add_timer_nodes()
392 qemu_fdt_setprop(ms->fdt, "/timer", "compatible", in fdt_add_timer_nodes()
395 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible", in fdt_add_timer_nodes()
398 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); in fdt_add_timer_nodes()
400 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", in fdt_add_timer_nodes()
412 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", in fdt_add_timer_nodes()
427 int addr_cells = 1; in fdt_add_cpu_nodes()
428 const MachineState *ms = MACHINE(vms); in fdt_add_cpu_nodes() local
430 int smp_cpus = ms->smp.cpus; in fdt_add_cpu_nodes()
437 * in the system, #address-cells can be set to 1, since in fdt_add_cpu_nodes()
454 qemu_fdt_add_subnode(ms->fdt, "/cpus"); in fdt_add_cpu_nodes()
455 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells); in fdt_add_cpu_nodes()
456 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); in fdt_add_cpu_nodes()
458 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { in fdt_add_cpu_nodes()
463 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_cpu_nodes()
464 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); in fdt_add_cpu_nodes()
465 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_cpu_nodes()
468 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) { in fdt_add_cpu_nodes()
469 qemu_fdt_setprop_string(ms->fdt, nodename, in fdt_add_cpu_nodes()
474 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", in fdt_add_cpu_nodes()
477 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", in fdt_add_cpu_nodes()
481 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { in fdt_add_cpu_nodes()
482 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", in fdt_add_cpu_nodes()
483 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); in fdt_add_cpu_nodes()
487 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", in fdt_add_cpu_nodes()
488 qemu_fdt_alloc_phandle(ms->fdt)); in fdt_add_cpu_nodes()
511 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); in fdt_add_cpu_nodes()
513 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) { in fdt_add_cpu_nodes()
517 if (ms->smp.threads > 1) { in fdt_add_cpu_nodes()
520 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads), in fdt_add_cpu_nodes()
521 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters, in fdt_add_cpu_nodes()
522 (cpu / ms->smp.threads) % ms->smp.cores, in fdt_add_cpu_nodes()
523 cpu % ms->smp.threads); in fdt_add_cpu_nodes()
527 cpu / (ms->smp.clusters * ms->smp.cores), in fdt_add_cpu_nodes()
528 (cpu / ms->smp.cores) % ms->smp.clusters, in fdt_add_cpu_nodes()
529 cpu % ms->smp.cores); in fdt_add_cpu_nodes()
531 qemu_fdt_add_path(ms->fdt, map_path); in fdt_add_cpu_nodes()
532 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); in fdt_add_cpu_nodes()
543 MachineState *ms = MACHINE(vms); in fdt_add_its_gic_node() local
545 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_its_gic_node()
548 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_its_gic_node()
549 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_its_gic_node()
551 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); in fdt_add_its_gic_node()
552 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1); in fdt_add_its_gic_node()
553 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_its_gic_node()
556 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); in fdt_add_its_gic_node()
562 MachineState *ms = MACHINE(vms); in fdt_add_v2m_gic_node() local
567 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_v2m_gic_node()
568 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_v2m_gic_node()
569 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_v2m_gic_node()
571 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0); in fdt_add_v2m_gic_node()
572 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_v2m_gic_node()
575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle); in fdt_add_v2m_gic_node()
581 MachineState *ms = MACHINE(vms); in fdt_add_gic_node() local
584 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt); in fdt_add_gic_node()
585 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle); in fdt_add_gic_node()
589 qemu_fdt_add_subnode(ms->fdt, nodename); in fdt_add_gic_node()
590 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); in fdt_add_gic_node()
591 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); in fdt_add_gic_node()
592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); in fdt_add_gic_node()
593 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); in fdt_add_gic_node()
594 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); in fdt_add_gic_node()
598 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_gic_node()
601 qemu_fdt_setprop_cell(ms->fdt, nodename, in fdt_add_gic_node()
604 if (nb_redist_regions == 1) { in fdt_add_gic_node()
605 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_gic_node()
611 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_gic_node()
621 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in fdt_add_gic_node()
628 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", in fdt_add_gic_node()
631 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_gic_node()
637 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in fdt_add_gic_node()
646 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in fdt_add_gic_node()
653 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle); in fdt_add_gic_node()
661 MachineState *ms = MACHINE(vms); in fdt_add_pmu_nodes() local
671 (1 << MACHINE(vms)->smp.cpus) - 1); in fdt_add_pmu_nodes()
674 qemu_fdt_add_subnode(ms->fdt, "/pmu"); in fdt_add_pmu_nodes()
677 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible", in fdt_add_pmu_nodes()
679 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts", in fdt_add_pmu_nodes()
688 MachineState *ms = MACHINE(vms); in create_acpi_ged() local
692 if (ms->ram_slots) { in create_acpi_ged()
696 if (ms->nvdimms_state->is_enabled) { in create_acpi_ged()
705 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base); in create_acpi_ged()
775 MachineState *ms = MACHINE(vms); in create_gic() local
780 unsigned int smp_cpus = ms->smp.cpus; in create_gic()
855 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); in create_gic()
861 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); in create_gic()
946 MachineState *ms = MACHINE(vms); in create_uart() local
955 qemu_fdt_add_subnode(ms->fdt, nodename); in create_uart()
957 qemu_fdt_setprop(ms->fdt, nodename, "compatible", in create_uart()
959 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_uart()
961 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in create_uart()
964 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", in create_uart()
966 qemu_fdt_setprop(ms->fdt, nodename, "clock-names", in create_uart()
970 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); in create_uart()
971 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename); in create_uart()
973 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename); in create_uart()
977 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); in create_uart()
978 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); in create_uart()
980 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path", in create_uart()
994 MachineState *ms = MACHINE(vms); in create_rtc() local
999 qemu_fdt_add_subnode(ms->fdt, nodename); in create_rtc()
1000 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); in create_rtc()
1001 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_rtc()
1003 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in create_rtc()
1006 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); in create_rtc()
1007 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); in create_rtc()
1020 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1); in virt_powerdown_req()
1027 gpio_key_dev = sysbus_create_simple("gpio-key", -1, in create_gpio_keys()
1044 #define SECURE_GPIO_RESET 1
1052 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL); in create_secure_gpio_pwr()
1089 MachineState *ms = MACHINE(vms); in create_gpio_devices() local
1100 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt); in create_gpio_devices()
1102 qemu_fdt_add_subnode(ms->fdt, nodename); in create_gpio_devices()
1103 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_gpio_devices()
1105 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat)); in create_gpio_devices()
1106 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2); in create_gpio_devices()
1107 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0); in create_gpio_devices()
1108 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in create_gpio_devices()
1111 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle); in create_gpio_devices()
1112 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk"); in create_gpio_devices()
1113 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle); in create_gpio_devices()
1117 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); in create_gpio_devices()
1118 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); in create_gpio_devices()
1124 create_gpio_keys(ms->fdt, pl061_dev, phandle); in create_gpio_devices()
1126 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle); in create_gpio_devices()
1134 MachineState *ms = MACHINE(vms); in create_virtio_devices() local
1178 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) { in create_virtio_devices()
1184 qemu_fdt_add_subnode(ms->fdt, nodename); in create_virtio_devices()
1185 qemu_fdt_setprop_string(ms->fdt, nodename, in create_virtio_devices()
1187 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_virtio_devices()
1189 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", in create_virtio_devices()
1192 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_virtio_devices()
1227 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); in virt_flash_create()
1263 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize, in virt_flash_map()
1273 MachineState *ms = MACHINE(vms); in virt_flash_fdt() local
1279 qemu_fdt_add_subnode(ms->fdt, nodename); in virt_flash_fdt()
1280 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); in virt_flash_fdt()
1281 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in virt_flash_fdt()
1284 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); in virt_flash_fdt()
1292 qemu_fdt_add_subnode(ms->fdt, nodename); in virt_flash_fdt()
1293 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); in virt_flash_fdt()
1294 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in virt_flash_fdt()
1296 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); in virt_flash_fdt()
1297 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); in virt_flash_fdt()
1298 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); in virt_flash_fdt()
1302 qemu_fdt_add_subnode(ms->fdt, nodename); in virt_flash_fdt()
1303 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); in virt_flash_fdt()
1304 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in virt_flash_fdt()
1306 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); in virt_flash_fdt()
1339 exit(1); in virt_firmware_init()
1347 exit(1); in virt_firmware_init()
1354 exit(1); in virt_firmware_init()
1363 MachineState *ms = MACHINE(vms); in create_fw_cfg() local
1370 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); in create_fw_cfg()
1373 qemu_fdt_add_subnode(ms->fdt, nodename); in create_fw_cfg()
1374 qemu_fdt_setprop_string(ms->fdt, nodename, in create_fw_cfg()
1376 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_fw_cfg()
1378 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_fw_cfg()
1383 static void create_pcie_irq_map(const MachineState *ms, in create_pcie_irq_map() argument
1400 pin + 1, /* PCI pin */ in create_pcie_irq_map()
1411 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", in create_pcie_irq_map()
1414 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", in create_pcie_irq_map()
1432 MachineState *ms = MACHINE(vms); in create_smmu() local
1453 qemu_fdt_add_subnode(ms->fdt, node); in create_smmu()
1454 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); in create_smmu()
1455 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size); in create_smmu()
1457 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts", in create_smmu()
1459 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, in create_smmu()
1463 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names, in create_smmu()
1466 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0); in create_smmu()
1468 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); in create_smmu()
1470 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); in create_smmu()
1478 MachineState *ms = MACHINE(vms); in create_virtio_iommu_dt_bindings() local
1481 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); in create_virtio_iommu_dt_bindings()
1485 qemu_fdt_add_subnode(ms->fdt, node); in create_virtio_iommu_dt_bindings()
1486 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat)); in create_virtio_iommu_dt_bindings()
1487 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", in create_virtio_iommu_dt_bindings()
1488 1, bdf << 8, 1, 0, 1, 0, in create_virtio_iommu_dt_bindings()
1489 1, 0, 1, 0); in create_virtio_iommu_dt_bindings()
1491 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1); in create_virtio_iommu_dt_bindings()
1492 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle); in create_virtio_iommu_dt_bindings()
1495 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map", in create_virtio_iommu_dt_bindings()
1497 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf); in create_virtio_iommu_dt_bindings()
1520 MachineState *ms = MACHINE(vms); in create_pcie() local
1521 MachineClass *mc = MACHINE_GET_CLASS(ms); in create_pcie()
1531 ecam_alias = g_new0(MemoryRegion, 1); in create_pcie()
1539 * (ie 1:1 mapping for that part of PCI MMIO space visible through in create_pcie()
1542 mmio_alias = g_new0(MemoryRegion, 1); in create_pcie()
1543 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); in create_pcie()
1550 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1); in create_pcie()
1575 qemu_fdt_add_subnode(ms->fdt, nodename); in create_pcie()
1576 qemu_fdt_setprop_string(ms->fdt, nodename, in create_pcie()
1578 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); in create_pcie()
1579 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); in create_pcie()
1580 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); in create_pcie()
1581 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); in create_pcie()
1582 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, in create_pcie()
1583 nr_pcie_buses - 1); in create_pcie()
1584 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); in create_pcie()
1587 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", in create_pcie()
1591 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", in create_pcie()
1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", in create_pcie()
1596 1, FDT_PCI_RANGE_IOPORT, 2, 0, in create_pcie()
1598 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, in create_pcie()
1600 1, FDT_PCI_RANGE_MMIO_64BIT, in create_pcie()
1604 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", in create_pcie()
1605 1, FDT_PCI_RANGE_IOPORT, 2, 0, in create_pcie()
1607 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, in create_pcie()
1611 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); in create_pcie()
1612 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename); in create_pcie()
1615 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt); in create_pcie()
1620 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", in create_pcie()
1658 MemoryRegion *tagram = g_new(MemoryRegion, 1); in create_tag_ram()
1668 MemoryRegion *secram = g_new(MemoryRegion, 1); in create_secure_ram()
1672 MachineState *ms = MACHINE(vms); in create_secure_ram() local
1679 qemu_fdt_add_subnode(ms->fdt, nodename); in create_secure_ram()
1680 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); in create_secure_ram()
1681 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); in create_secure_ram()
1682 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled"); in create_secure_ram()
1683 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay"); in create_secure_ram()
1696 MachineState *ms = MACHINE(board); in machvirt_dtb() local
1700 return ms->fdt; in machvirt_dtb()
1706 MachineState *ms = MACHINE(vms); in virt_build_smbios() local
1722 mem_array.length = ms->ram_size; in virt_build_smbios()
1724 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1, in virt_build_smbios()
1742 MachineState *ms = MACHINE(vms); in virt_machine_done() local
1755 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc", in virt_machine_done()
1760 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) { in virt_machine_done()
1761 exit(1); in virt_machine_done()
1841 vms->highest_gpa = base - 1; in virt_set_high_memmap()
1848 MachineState *ms = MACHINE(vms); in virt_set_memmap() local
1858 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { in virt_set_memmap()
1860 ms->ram_slots); in virt_set_memmap()
1875 * is aligned on 1GiB. We never put the high IO region below 256GiB in virt_set_memmap()
1877 * The device region size assumes 1GiB page max alignment per slot. in virt_set_memmap()
1880 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); in virt_set_memmap()
1881 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; in virt_set_memmap()
1899 vms->highest_gpa = memtop - 1; in virt_set_memmap()
1904 machine_memory_devices_init(ms, device_memory_base, device_memory_size); in virt_set_memmap()
1918 exit(1); in finalize_gic_version_do()
1947 exit(1); in finalize_gic_version_do()
1961 exit(1); in finalize_gic_version_do()
1967 exit(1); in finalize_gic_version_do()
1974 exit(1); in finalize_gic_version_do()
1979 exit(1); in finalize_gic_version_do()
2004 exit(1); in finalize_gic_version()
2028 exit(1); in finalize_gic_version()
2059 MemoryRegion *pvtime = g_new(MemoryRegion, 1); in virt_cpu_post_init()
2070 exit(1); in virt_cpu_post_init()
2100 exit(1); in virt_cpu_post_init()
2162 secure_sysmem = g_new(MemoryRegion, 1); in machvirt_init()
2165 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1); in machvirt_init()
2211 exit(1); in machvirt_init()
2218 exit(1); in machvirt_init()
2225 exit(1); in machvirt_init()
2232 exit(1); in machvirt_init()
2308 exit(1); in machvirt_init()
2311 tag_sysmem = g_new(MemoryRegion, 1); in machvirt_init()
2316 secure_tag_sysmem = g_new(MemoryRegion, 1); in machvirt_init()
2323 0, tag_sysmem, -1); in machvirt_init()
2337 exit(1); in machvirt_init()
2342 exit(1); in machvirt_init()
2389 Chardev *serial1 = serial_hd(1); in machvirt_init()
2398 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true); in machvirt_init()
2454 vms->bootinfo.board_id = -1; in machvirt_init()
2806 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) in virt_cpu_index_to_props() argument
2808 MachineClass *mc = MACHINE_GET_CLASS(ms); in virt_cpu_index_to_props()
2809 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); in virt_cpu_index_to_props()
2815 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) in virt_get_default_cpu_node_id() argument
2817 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id; in virt_get_default_cpu_node_id()
2819 return socket_id % ms->numa_state->num_nodes; in virt_get_default_cpu_node_id()
2822 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) in virt_possible_cpu_arch_ids() argument
2825 unsigned int max_cpus = ms->smp.max_cpus; in virt_possible_cpu_arch_ids()
2826 VirtMachineState *vms = VIRT_MACHINE(ms); in virt_possible_cpu_arch_ids()
2829 if (ms->possible_cpus) { in virt_possible_cpu_arch_ids()
2830 assert(ms->possible_cpus->len == max_cpus); in virt_possible_cpu_arch_ids()
2831 return ms->possible_cpus; in virt_possible_cpu_arch_ids()
2834 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + in virt_possible_cpu_arch_ids()
2836 ms->possible_cpus->len = max_cpus; in virt_possible_cpu_arch_ids()
2837 for (n = 0; n < ms->possible_cpus->len; n++) { in virt_possible_cpu_arch_ids()
2838 ms->possible_cpus->cpus[n].type = ms->cpu_type; in virt_possible_cpu_arch_ids()
2839 ms->possible_cpus->cpus[n].arch_id = in virt_possible_cpu_arch_ids()
2843 ms->possible_cpus->cpus[n].props.has_socket_id = true; in virt_possible_cpu_arch_ids()
2844 ms->possible_cpus->cpus[n].props.socket_id = in virt_possible_cpu_arch_ids()
2845 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); in virt_possible_cpu_arch_ids()
2846 ms->possible_cpus->cpus[n].props.has_cluster_id = true; in virt_possible_cpu_arch_ids()
2847 ms->possible_cpus->cpus[n].props.cluster_id = in virt_possible_cpu_arch_ids()
2848 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; in virt_possible_cpu_arch_ids()
2849 ms->possible_cpus->cpus[n].props.has_core_id = true; in virt_possible_cpu_arch_ids()
2850 ms->possible_cpus->cpus[n].props.core_id = in virt_possible_cpu_arch_ids()
2851 (n / ms->smp.threads) % ms->smp.cores; in virt_possible_cpu_arch_ids()
2852 ms->possible_cpus->cpus[n].props.has_thread_id = true; in virt_possible_cpu_arch_ids()
2853 ms->possible_cpus->cpus[n].props.thread_id = in virt_possible_cpu_arch_ids()
2854 n % ms->smp.threads; in virt_possible_cpu_arch_ids()
2856 return ms->possible_cpus; in virt_possible_cpu_arch_ids()
2863 const MachineState *ms = MACHINE(hotplug_dev); in virt_memory_pre_plug() local
2877 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { in virt_memory_pre_plug()
2889 MachineState *ms = MACHINE(hotplug_dev); in virt_memory_plug() local
2895 nvdimm_plug(ms->nvdimms_state); in virt_memory_plug()
2928 base_memmap[VIRT_GIC_ITS].size - 1; in virt_machine_device_pre_plug_cb()
2933 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; in virt_machine_device_pre_plug_cb()
3059 static int virt_kvm_type(MachineState *ms, const char *type_str) in virt_kvm_type() argument
3061 VirtMachineState *vms = VIRT_MACHINE(ms); in virt_kvm_type()
3065 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa); in virt_kvm_type()
3084 return -1; in virt_kvm_type()
3094 static int virt_hvf_get_physical_address_range(MachineState *ms) in virt_hvf_get_physical_address_range() argument
3096 VirtMachineState *vms = VIRT_MACHINE(ms); in virt_hvf_get_physical_address_range()
3121 return -1; in virt_hvf_get_physical_address_range()
3173 mc->no_cdrom = 1; in virt_machine_class_init()
3175 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ in virt_machine_class_init()
3429 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */ in virt_machine_9_1_options()
3432 DEFINE_VIRT_MACHINE(9, 1)
3462 DEFINE_VIRT_MACHINE(8, 1)
3487 DEFINE_VIRT_MACHINE(7, 1)
3518 DEFINE_VIRT_MACHINE(6, 1)
3545 DEFINE_VIRT_MACHINE(5, 1)
3578 DEFINE_VIRT_MACHINE(4, 1)
3592 DEFINE_VIRT_MACHINE(3, 1)
3659 /* Stick with 1K pages for migration compatibility */ in virt_machine_2_7_options()