Lines Matching +full:imx35 +full:- +full:spdif
1 // SPDX-License-Identifier: GPL-2.0
27 #include "imx-pcm.h"
74 * SPDIF control structure
99 * struct fsl_spdif_priv - Freescale SPDIF private data
100 * @soc: SPDIF soc data
101 * @fsl_spdif_control: SPDIF control data
216 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) in fsl_spdif_can_set_clk_rate() argument
218 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; in fsl_spdif_can_set_clk_rate()
224 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
225 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
231 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
234 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
236 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) { in spdif_irq_dpll_lock()
237 snd_ctl_notify(spdif_priv->snd_card, in spdif_irq_dpll_lock()
239 &spdif_priv->rxrate_kcontrol->id); in spdif_irq_dpll_lock()
246 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_sym_error()
247 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_sym_error()
249 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); in spdif_irq_sym_error()
252 if (!spdif_priv->dpll_locked) in spdif_irq_sym_error()
259 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full()
260 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uqrx_full()
261 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uqrx_full()
266 pos = &ctrl->upos; in spdif_irq_uqrx_full()
271 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
276 dev_err(&pdev->dev, "unsupported channel name\n"); in spdif_irq_uqrx_full()
280 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); in spdif_irq_uqrx_full()
285 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); in spdif_irq_uqrx_full()
290 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
291 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
292 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
298 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync()
299 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_sync()
301 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); in spdif_irq_uq_sync()
304 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
308 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
314 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err()
315 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uq_err()
316 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_err()
319 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); in spdif_irq_uq_err()
326 ctrl->ready_buf = 0; in spdif_irq_uq_err()
327 ctrl->upos = 0; in spdif_irq_uq_err()
328 ctrl->qpos = 0; in spdif_irq_uq_err()
331 /* Get spdif interrupt status and clear the interrupt */
334 struct regmap *regmap = spdif_priv->regmap; in spdif_intr_status_clear()
348 struct platform_device *pdev = spdif_priv->pdev; in spdif_isr()
357 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); in spdif_isr()
360 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); in spdif_isr()
363 dev_dbg(&pdev->dev, "isr: cstatus new\n"); in spdif_isr()
366 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); in spdif_isr()
372 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); in spdif_isr()
378 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); in spdif_isr()
384 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); in spdif_isr()
393 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); in spdif_isr()
396 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); in spdif_isr()
403 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); in spdif_isr()
407 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); in spdif_isr()
414 struct regmap *regmap = spdif_priv->regmap; in spdif_softreset()
427 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
436 return -EBUSY; in spdif_softreset()
442 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
443 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
448 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status()
449 struct regmap *regmap = spdif_priv->regmap; in spdif_write_channel_status()
450 struct platform_device *pdev = spdif_priv->pdev; in spdif_write_channel_status()
453 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
454 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
455 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
458 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); in spdif_write_channel_status()
460 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
463 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); in spdif_write_channel_status()
465 if (spdif_priv->soc->cchannel_192b) { in spdif_write_channel_status()
466 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | in spdif_write_channel_status()
467 (bitrev8(ctrl->ch_status[1]) << 16) | in spdif_write_channel_status()
468 (bitrev8(ctrl->ch_status[2]) << 8) | in spdif_write_channel_status()
469 bitrev8(ctrl->ch_status[3]); in spdif_write_channel_status()
483 /* Set SPDIF PhaseConfig register for rx clock */
487 struct regmap *regmap = spdif_priv->regmap; in spdif_set_rx_clksrc()
488 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc()
491 return -EINVAL; in spdif_set_rx_clksrc()
507 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate()
508 struct regmap *regmap = spdif_priv->regmap; in spdif_set_sample_rate()
509 struct platform_device *pdev = spdif_priv->pdev; in spdif_set_sample_rate()
550 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); in spdif_set_sample_rate()
551 return -EINVAL; in spdif_set_sample_rate()
558 clk = spdif_priv->txclk_src[rate]; in spdif_set_sample_rate()
560 dev_err(&pdev->dev, "tx clock source is out of range\n"); in spdif_set_sample_rate()
561 return -EINVAL; in spdif_set_sample_rate()
564 txclk_df = spdif_priv->txclk_df[rate]; in spdif_set_sample_rate()
566 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); in spdif_set_sample_rate()
567 return -EINVAL; in spdif_set_sample_rate()
570 sysclk_df = spdif_priv->sysclk_df[rate]; in spdif_set_sample_rate()
576 ret = clk_set_rate(spdif_priv->txclk[clk], in spdif_set_sample_rate()
579 dev_err(&pdev->dev, "failed to set tx clock rate\n"); in spdif_set_sample_rate()
584 dev_dbg(&pdev->dev, "expected clock rate = %d\n", in spdif_set_sample_rate()
586 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", in spdif_set_sample_rate()
587 clk_get_rate(spdif_priv->txclk[clk])); in spdif_set_sample_rate()
599 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", in spdif_set_sample_rate()
600 spdif_priv->txrate[rate], sample_rate); in spdif_set_sample_rate()
610 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_startup()
611 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_startup()
619 dev_err(&pdev->dev, "failed to soft reset\n"); in fsl_spdif_startup()
627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_startup()
641 /* Power up SPDIF module */ in fsl_spdif_startup()
652 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_shutdown()
655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_shutdown()
669 /* Power down SPDIF module only if tx&rx are both inactive */ in fsl_spdif_shutdown()
679 struct platform_device *pdev = spdif_priv->pdev; in spdif_reparent_rootclk()
688 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; in spdif_reparent_rootclk()
692 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, in spdif_reparent_rootclk()
693 spdif_priv->pll11k_clk, sample_rate); in spdif_reparent_rootclk()
706 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params()
707 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_hw_params()
711 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_hw_params()
714 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", in fsl_spdif_hw_params()
721 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", in fsl_spdif_hw_params()
741 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_trigger()
742 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_spdif_trigger()
762 return -EINVAL; in fsl_spdif_trigger()
769 * FSL SPDIF IEC958 controller(mixer) functions
781 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_spdif_info()
782 uinfo->count = 1; in fsl_spdif_info()
792 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get()
794 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
795 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
796 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
797 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
807 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put()
809 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
810 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
811 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
812 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
825 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_capture_get()
830 return -EAGAIN; in fsl_spdif_capture_get()
833 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
834 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
835 ucontrol->value.iec958.status[2] = cstatus & 0xFF; in fsl_spdif_capture_get()
838 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
839 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
840 ucontrol->value.iec958.status[5] = cstatus & 0xFF; in fsl_spdif_capture_get()
857 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get()
859 int ret = -EAGAIN; in fsl_spdif_subcode_get()
861 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
862 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
863 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
864 memcpy(&ucontrol->value.iec958.subcode[0], in fsl_spdif_subcode_get()
865 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
868 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
873 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
877 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_spdif_qinfo()
878 uinfo->count = SPDIF_QSUB_SIZE; in fsl_spdif_qinfo()
889 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget()
891 int ret = -EAGAIN; in fsl_spdif_qget()
893 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
894 if (ctrl->ready_buf) { in fsl_spdif_qget()
895 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
896 memcpy(&ucontrol->value.bytes.data[0], in fsl_spdif_qget()
897 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
900 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
911 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_vbit_get()
915 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; in fsl_spdif_rx_vbit_get()
926 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_get()
931 val = 1 - val; in fsl_spdif_tx_vbit_get()
932 ucontrol->value.integer.value[0] = val; in fsl_spdif_tx_vbit_get()
942 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_tx_vbit_put()
943 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; in fsl_spdif_tx_vbit_put()
955 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_get()
960 ucontrol->value.integer.value[0] = val; in fsl_spdif_rx_rcm_get()
970 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_rx_rcm_put()
971 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); in fsl_spdif_rx_rcm_put()
974 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
976 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; in fsl_spdif_rx_rcm_put()
989 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; in fsl_spdif_bypass_get()
999 struct snd_soc_card *card = dai->component->card; in fsl_spdif_bypass_put()
1000 bool set = (ucontrol->value.integer.value[0] != 0); in fsl_spdif_bypass_put()
1001 struct regmap *regmap = priv->regmap; in fsl_spdif_bypass_put()
1006 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); in fsl_spdif_bypass_put()
1008 if (priv->bypass == set) in fsl_spdif_bypass_put()
1012 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); in fsl_spdif_bypass_put()
1013 return -EBUSY; in fsl_spdif_bypass_put()
1016 pm_runtime_get_sync(dai->dev); in fsl_spdif_bypass_put()
1026 /* Power up SPDIF module */ in fsl_spdif_bypass_put()
1029 /* Power down SPDIF module, disable TX */ in fsl_spdif_bypass_put()
1038 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); in fsl_spdif_bypass_put()
1040 priv->bypass = set; in fsl_spdif_bypass_put()
1041 pm_runtime_put_sync(dai->dev); in fsl_spdif_bypass_put()
1050 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in fsl_spdif_rxrate_info()
1051 uinfo->count = 1; in fsl_spdif_rxrate_info()
1052 uinfo->value.integer.min = 16000; in fsl_spdif_rxrate_info()
1053 uinfo->value.integer.max = 192000; in fsl_spdif_rxrate_info()
1062 /* Get RX data clock rate given the SPDIF bus_clk */
1066 struct regmap *regmap = spdif_priv->regmap; in spdif_get_rxclk_rate()
1067 struct platform_device *pdev = spdif_priv->pdev; in spdif_get_rxclk_rate()
1079 busclk_freq = clk_get_rate(spdif_priv->sysclk); in spdif_get_rxclk_rate()
1086 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); in spdif_get_rxclk_rate()
1087 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); in spdif_get_rxclk_rate()
1088 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); in spdif_get_rxclk_rate()
1105 if (spdif_priv->dpll_locked) in fsl_spdif_rxrate_get()
1108 ucontrol->value.integer.value[0] = rate; in fsl_spdif_rxrate_get()
1116 * 0 Non-CD data
1123 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_get()
1127 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; in fsl_spdif_usync_get()
1135 * 0 Non-CD data
1142 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_put()
1143 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; in fsl_spdif_usync_put()
1150 /* FSL SPDIF IEC958 controller defines */
1182 .name = "IEC958 Q-subcode Capture Default",
1191 .name = "IEC958 RX V-Bit Errors",
1199 .name = "IEC958 TX V-Bit",
1255 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, in fsl_spdif_dai_probe()
1256 &spdif_private->dma_params_rx); in fsl_spdif_dai_probe()
1260 if (spdif_private->soc->raw_capture_mode) in fsl_spdif_dai_probe()
1264 spdif_private->snd_card = dai->component->card->snd_card; in fsl_spdif_dai_probe()
1265 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card, in fsl_spdif_dai_probe()
1267 if (!spdif_private->rxrate_kcontrol) in fsl_spdif_dai_probe()
1268 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n", in fsl_spdif_dai_probe()
1272 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, in fsl_spdif_dai_probe()
1288 .stream_name = "CPU-Playback",
1295 .stream_name = "CPU-Capture",
1305 .name = "fsl-spdif",
1309 /* FSL SPDIF REGMAP */
1432 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); in fsl_spdif_txclk_caldiv()
1456 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1457 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1458 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1462 sub = (u64)(arate - rate[index]) * 100000; in fsl_spdif_txclk_caldiv()
1467 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1468 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1469 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1472 sub = (u64)(rate[index] - arate) * 100000; in fsl_spdif_txclk_caldiv()
1477 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1478 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1479 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1493 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_probe_txclk()
1494 struct device *dev = &pdev->dev; in fsl_spdif_probe_txclk()
1500 clk = spdif_priv->txclk[i]; in fsl_spdif_probe_txclk()
1514 spdif_priv->txclk_src[index] = i; in fsl_spdif_probe_txclk()
1522 spdif_priv->txclk_src[index], rate[index]); in fsl_spdif_probe_txclk()
1524 spdif_priv->txclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1525 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) in fsl_spdif_probe_txclk()
1527 spdif_priv->sysclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1529 rate[index], spdif_priv->txrate[index]); in fsl_spdif_probe_txclk()
1543 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); in fsl_spdif_probe()
1545 return -ENOMEM; in fsl_spdif_probe()
1547 spdif_priv->pdev = pdev; in fsl_spdif_probe()
1549 spdif_priv->soc = of_device_get_match_data(&pdev->dev); in fsl_spdif_probe()
1552 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); in fsl_spdif_probe()
1553 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); in fsl_spdif_probe()
1554 spdif_priv->cpu_dai_drv.playback.formats = in fsl_spdif_probe()
1555 spdif_priv->soc->tx_formats; in fsl_spdif_probe()
1562 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); in fsl_spdif_probe()
1563 if (IS_ERR(spdif_priv->regmap)) { in fsl_spdif_probe()
1564 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_spdif_probe()
1565 return PTR_ERR(spdif_priv->regmap); in fsl_spdif_probe()
1568 for (i = 0; i < spdif_priv->soc->interrupts; i++) { in fsl_spdif_probe()
1573 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, in fsl_spdif_probe()
1574 dev_name(&pdev->dev), spdif_priv); in fsl_spdif_probe()
1576 dev_err(&pdev->dev, "could not claim irq %u\n", irq); in fsl_spdif_probe()
1583 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); in fsl_spdif_probe()
1584 if (IS_ERR(spdif_priv->txclk[i])) { in fsl_spdif_probe()
1585 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); in fsl_spdif_probe()
1586 return PTR_ERR(spdif_priv->txclk[i]); in fsl_spdif_probe()
1591 spdif_priv->sysclk = spdif_priv->txclk[5]; in fsl_spdif_probe()
1592 if (IS_ERR(spdif_priv->sysclk)) { in fsl_spdif_probe()
1593 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); in fsl_spdif_probe()
1594 return PTR_ERR(spdif_priv->sysclk); in fsl_spdif_probe()
1598 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1599 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1600 dev_err(&pdev->dev, "no core clock in devicetree\n"); in fsl_spdif_probe()
1601 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1604 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); in fsl_spdif_probe()
1605 if (IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_probe()
1606 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); in fsl_spdif_probe()
1609 spdif_priv->rxclk = spdif_priv->txclk[1]; in fsl_spdif_probe()
1610 if (IS_ERR(spdif_priv->rxclk)) { in fsl_spdif_probe()
1611 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); in fsl_spdif_probe()
1612 return PTR_ERR(spdif_priv->rxclk); in fsl_spdif_probe()
1614 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; in fsl_spdif_probe()
1616 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, in fsl_spdif_probe()
1617 &spdif_priv->pll11k_clk); in fsl_spdif_probe()
1620 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1621 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1624 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1626 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1627 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1628 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()
1631 spdif_priv->dpll_locked = false; in fsl_spdif_probe()
1633 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; in fsl_spdif_probe()
1634 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; in fsl_spdif_probe()
1635 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; in fsl_spdif_probe()
1636 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; in fsl_spdif_probe()
1639 dev_set_drvdata(&pdev->dev, spdif_priv); in fsl_spdif_probe()
1640 pm_runtime_enable(&pdev->dev); in fsl_spdif_probe()
1641 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_probe()
1649 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); in fsl_spdif_probe()
1653 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, in fsl_spdif_probe()
1654 &spdif_priv->cpu_dai_drv, 1); in fsl_spdif_probe()
1656 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); in fsl_spdif_probe()
1663 pm_runtime_disable(&pdev->dev); in fsl_spdif_probe()
1669 pm_runtime_disable(&pdev->dev); in fsl_spdif_remove()
1679 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); in fsl_spdif_runtime_suspend()
1681 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_suspend()
1682 &spdif_priv->regcache_srpc); in fsl_spdif_runtime_suspend()
1683 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_runtime_suspend()
1686 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_suspend()
1688 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_suspend()
1689 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_suspend()
1690 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1701 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1707 if (!IS_ERR(spdif_priv->spbaclk)) { in fsl_spdif_runtime_resume()
1708 ret = clk_prepare_enable(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1716 ret = clk_prepare_enable(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1721 regcache_cache_only(spdif_priv->regmap, false); in fsl_spdif_runtime_resume()
1722 regcache_mark_dirty(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1724 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_runtime_resume()
1726 spdif_priv->regcache_srpc); in fsl_spdif_runtime_resume()
1728 ret = regcache_sync(spdif_priv->regmap); in fsl_spdif_runtime_resume()
1735 for (i--; i >= 0; i--) in fsl_spdif_runtime_resume()
1736 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_runtime_resume()
1737 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_runtime_resume()
1738 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_runtime_resume()
1740 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1754 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, },
1755 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, },
1756 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, },
1757 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, },
1758 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, },
1759 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, },
1766 .name = "fsl-spdif-dai",
1779 MODULE_ALIAS("platform:fsl-spdif-dai");