Lines Matching +full:mux +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677.c -- RT5677 ALSA SoC audio codec driver
29 #include <sound/soc-dapm.h>
35 #include "rt5677-spi.h"
552 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
563 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_write_addr()
566 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
568 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_write_addr()
571 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
575 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_write_addr()
578 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
582 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, in rt5677_dsp_mode_i2c_write_addr()
585 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
589 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, in rt5677_dsp_mode_i2c_write_addr()
592 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
596 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_write_addr()
599 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
604 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
610 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
621 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_read_addr()
625 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
627 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_read_addr()
630 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
634 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_read_addr()
637 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
641 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_read_addr()
644 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
648 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); in rt5677_dsp_mode_i2c_read_addr()
649 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); in rt5677_dsp_mode_i2c_read_addr()
653 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
659 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
675 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_dsp_mode()
699 rt5677->is_dsp_mode = true; in rt5677_set_dsp_mode()
701 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_dsp_mode()
703 rt5677->is_dsp_mode = false; in rt5677_set_dsp_mode()
710 snd_soc_component_get_dapm(rt5677->component); in rt5677_set_vad_source()
719 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, in rt5677_set_vad_source()
723 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_set_vad_source()
727 regmap_write(rt5677->regmap, RT5677_GLB_CLK2, in rt5677_set_vad_source()
731 regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f); in rt5677_set_vad_source()
733 regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5); in rt5677_set_vad_source()
738 regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4, in rt5677_set_vad_source()
741 /* Minimum frame level within a pre-determined duration = 32 frames in rt5677_set_vad_source()
744 * SAD Buffer Over-Writing = enable in rt5677_set_vad_source()
751 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, in rt5677_set_vad_source()
757 /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it in rt5677_set_vad_source()
764 regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4, in rt5677_set_vad_source()
770 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_vad_source()
777 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_vad_source()
787 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, in rt5677_set_vad_source()
800 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_set_vad_source()
814 struct snd_soc_component *component = rt5677->component; in rt5677_parse_and_load_dsp()
821 return -ENOMEM; in rt5677_parse_and_load_dsp()
827 if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1)) in rt5677_parse_and_load_dsp()
828 dev_err(component->dev, "Wrong ELF header prefix\n"); in rt5677_parse_and_load_dsp()
829 if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr)) in rt5677_parse_and_load_dsp()
830 dev_err(component->dev, "Wrong ELF header size\n"); in rt5677_parse_and_load_dsp()
831 if (elf_hdr->e_machine != EM_XTENSA) in rt5677_parse_and_load_dsp()
832 dev_err(component->dev, "Wrong DSP code file\n"); in rt5677_parse_and_load_dsp()
834 if (len < elf_hdr->e_phoff) in rt5677_parse_and_load_dsp()
835 return -ENOMEM; in rt5677_parse_and_load_dsp()
836 pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff); in rt5677_parse_and_load_dsp()
837 for (i = 0; i < elf_hdr->e_phnum; i++) { in rt5677_parse_and_load_dsp()
839 if (pr_hdr->p_paddr && pr_hdr->p_filesz) { in rt5677_parse_and_load_dsp()
840 dev_info(component->dev, "Load 0x%x bytes to 0x%x\n", in rt5677_parse_and_load_dsp()
841 pr_hdr->p_filesz, pr_hdr->p_paddr); in rt5677_parse_and_load_dsp()
843 ret = rt5677_spi_write(pr_hdr->p_paddr, in rt5677_parse_and_load_dsp()
844 buf + pr_hdr->p_offset, in rt5677_parse_and_load_dsp()
845 pr_hdr->p_filesz); in rt5677_parse_and_load_dsp()
847 dev_err(component->dev, "Load firmware failed %d\n", in rt5677_parse_and_load_dsp()
858 struct device *dev = rt5677->component->dev; in rt5677_load_dsp_from_file()
867 dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size); in rt5677_load_dsp_from_file()
869 ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size); in rt5677_load_dsp_from_file()
877 rt5677->dsp_vad_en_request = on; in rt5677_set_dsp_vad()
878 rt5677->dsp_vad_en = on; in rt5677_set_dsp_vad()
881 return -ENXIO; in rt5677_set_dsp_vad()
883 schedule_delayed_work(&rt5677->dsp_work, 0); in rt5677_set_dsp_vad()
892 bool enable = rt5677->dsp_vad_en; in rt5677_dsp_work()
896 dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n", in rt5677_dsp_work()
917 regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val); in rt5677_dsp_work()
923 dev_err(rt5677->component->dev, "DSP Boot Timed Out!"); in rt5677_dsp_work()
938 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_dsp_work()
944 mutex_lock(&rt5677->irq_lock); in rt5677_dsp_work()
946 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, in rt5677_dsp_work()
952 regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184); in rt5677_dsp_work()
955 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_dsp_work()
958 mutex_unlock(&rt5677->irq_lock); in rt5677_dsp_work()
962 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
963 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
965 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
984 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request; in rt5677_dsp_vad_get()
994 rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]); in rt5677_dsp_vad_put()
1076 * set_dmic_clk - Set parameter of dmic.
1088 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
1092 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, in set_dmic_clk()
1096 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
1098 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, in set_dmic_clk()
1106 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_sys_clk_from_pll()
1110 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); in is_sys_clk_from_pll()
1121 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_using_asrc()
1125 if (source->reg == RT5677_ASRC_1) { in is_using_asrc()
1126 switch (source->shift) { in is_using_asrc()
1147 switch (source->shift) { in is_using_asrc()
1189 regmap_read(rt5677->regmap, reg, &val); in is_using_asrc()
1204 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in can_use_asrc()
1207 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) in can_use_asrc()
1214 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1255 return -EINVAL; in rt5677_sel_asrc_clk_src()
1278 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, in rt5677_sel_asrc_clk_src()
1307 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, in rt5677_sel_asrc_clk_src()
1336 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, in rt5677_sel_asrc_clk_src()
1353 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, in rt5677_sel_asrc_clk_src()
1370 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, in rt5677_sel_asrc_clk_src()
1377 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1383 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1389 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1395 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1399 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, in rt5677_sel_asrc_clk_src()
1409 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in rt5677_dmic_use_asrc()
1413 switch (source->shift) { in rt5677_dmic_use_asrc()
1415 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1421 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1427 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1433 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1439 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1445 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1737 /* Mux */
1738 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1751 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1764 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1789 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1814 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1839 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1879 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1905 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1952 /* Stereo2 ADC Source */ /* MX-26 [0] */
1964 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1990 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
2002 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
2014 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
2026 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
2038 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
2051 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
2063 /* InBound0/1 Source */ /* MX-A3 [14:12] */
2076 /* InBound2/3 Source */ /* MX-A3 [10:8] */
2089 /* InBound4/5 Source */ /* MX-A3 [6:4] */
2102 /* InBound6 Source */ /* MX-A3 [2:0] */
2115 /* InBound7 Source */ /* MX-A4 [14:12] */
2128 /* InBound8 Source */ /* MX-A4 [10:8] */
2141 /* InBound9 Source */ /* MX-A4 [6:4] */
2154 /* VAD Source */ /* MX-9F [6:4] */
2167 /* Sidetone Source */ /* MX-13 [11:9] */
2179 /* DAC1/2 Source */ /* MX-15 [1:0] */
2191 /* DAC3 Source */ /* MX-15 [5:4] */
2203 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2236 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2262 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2288 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2314 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2340 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2360 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2421 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2434 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2447 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2448 MX-3F[14:12][10:8][6:4][2:0]
2449 MX-43[14:12][10:8][6:4][2:0]
2450 MX-44[14:12][10:8][6:4][2:0] */
2570 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst1_event()
2575 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2580 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2594 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst2_event()
2599 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2604 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2618 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll1_event()
2623 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); in rt5677_set_pll1_event()
2627 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); in rt5677_set_pll1_event()
2640 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll2_event()
2645 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); in rt5677_set_pll2_event()
2649 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); in rt5677_set_pll2_event()
2662 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_micbias1_event()
2667 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2674 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2689 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if1_adc_tdm_event()
2695 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); in rt5677_if1_adc_tdm_event()
2697 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, in rt5677_if1_adc_tdm_event()
2712 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if2_adc_tdm_event()
2718 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); in rt5677_if2_adc_tdm_event()
2720 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, in rt5677_if2_adc_tdm_event()
2735 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_vref_event()
2741 !rt5677->is_vref_slow) { in rt5677_vref_event()
2743 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_vref_event()
2746 rt5677->is_vref_slow = true; in rt5677_vref_event()
2884 /* ADC Mux */
2885 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2887 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2889 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2891 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2893 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2895 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2897 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2899 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2901 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2903 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2905 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2907 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2909 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2911 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2913 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2915 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2917 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2919 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2921 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2977 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2979 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2981 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2983 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2985 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2987 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2989 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2991 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2993 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2995 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2997 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2999 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
3089 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
3091 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
3093 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
3095 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
3097 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
3099 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
3101 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
3103 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
3105 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
3108 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
3110 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
3112 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
3114 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
3116 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
3118 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
3120 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
3122 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
3124 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
3127 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
3129 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
3131 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
3133 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
3135 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
3137 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
3140 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
3142 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
3144 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
3146 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
3148 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
3150 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
3152 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
3154 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3157 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
3159 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
3161 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
3163 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
3165 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
3167 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
3169 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
3171 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
3187 /* Sidetone Mux */
3188 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3193 /* VAD Mux*/
3194 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3220 /* DAC Mux */
3221 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3223 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3225 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3227 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3230 /* DAC2 channel Mux */
3231 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3233 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3236 /* DAC3 channel Mux */
3237 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3239 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3242 /* DAC4 channel Mux */
3243 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3245 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3306 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3308 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3310 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3312 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3342 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3343 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3344 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3345 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3346 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3347 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3409 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3410 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3411 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3412 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3414 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3415 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3416 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3417 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3419 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3420 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3421 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3422 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3424 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3425 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3426 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3427 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3429 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3430 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3431 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3432 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3434 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3435 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3436 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3437 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3442 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3443 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3444 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3446 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3447 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3448 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3450 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3451 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3452 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3454 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3455 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3456 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3458 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3459 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3460 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3462 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3463 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3464 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3466 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3467 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3468 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3470 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3471 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3472 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3474 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3475 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3476 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3478 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3479 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3480 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3482 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3483 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3484 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3486 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3487 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3488 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3490 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3491 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3492 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3493 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3504 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3505 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3506 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3507 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3512 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3513 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3515 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3524 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3525 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3526 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3527 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3538 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3539 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3540 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3541 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3552 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3553 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3557 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3558 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3565 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3566 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3567 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3568 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3569 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3571 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3572 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3573 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3575 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3576 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3578 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3579 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3580 { "IF1 ADC3 Mux", "OB45", "OB45" },
3582 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3583 { "IF1 ADC4 Mux", "OB67", "OB67" },
3584 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3586 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3587 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3588 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3589 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3591 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3592 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3593 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3594 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3596 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3597 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3598 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3599 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3601 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3602 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3603 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3604 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3606 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3607 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3608 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3609 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3611 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3612 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3613 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3614 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3615 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3616 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3617 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3618 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3621 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3623 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3624 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3625 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3627 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3628 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3630 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3631 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3632 { "IF2 ADC3 Mux", "OB45", "OB45" },
3634 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3635 { "IF2 ADC4 Mux", "OB67", "OB67" },
3636 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3638 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3639 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3640 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3641 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3643 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3644 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3645 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3646 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3648 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3649 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3650 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3651 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3653 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3654 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3655 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3656 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3658 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3659 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3660 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3661 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3663 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3664 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3665 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3666 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3667 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3668 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3669 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3670 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3673 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3675 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3676 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3677 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3678 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3679 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3680 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3681 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3682 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3685 { "AIF3TX", NULL, "IF3 ADC Mux" },
3687 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3688 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3689 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3690 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3691 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3692 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3693 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3694 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3697 { "AIF4TX", NULL, "IF4 ADC Mux" },
3699 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3700 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3701 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3703 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3704 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3706 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3707 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3708 { "SLB ADC3 Mux", "OB45", "OB45" },
3710 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3711 { "SLB ADC4 Mux", "OB67", "OB67" },
3712 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3715 { "SLBTX", NULL, "SLB ADC1 Mux" },
3716 { "SLBTX", NULL, "SLB ADC2 Mux" },
3717 { "SLBTX", NULL, "SLB ADC3 Mux" },
3718 { "SLBTX", NULL, "SLB ADC4 Mux" },
3720 { "DSPTX", NULL, "IB01 Bypass Mux" },
3722 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3723 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3724 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3725 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3726 /* The IB01 Mux controls the source for InBound0 and InBound1.
3727 * When the mux option "VAD ADC/DAC1 FS" is selected, "VAD ADC" goes to
3732 * connecting the common widget to IB01 Mux causes the issue where
3733 * there is an active path going from system playback -> "DAC1 FS" ->
3734 * IB01 Mux -> DSP Buffer -> hotword stream. This wrong path confuses
3737 { "IB01 Mux", "VAD ADC/DAC1 FS", "VAD ADC Mux" },
3739 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3740 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3742 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3743 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3744 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3745 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3746 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3747 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3749 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3750 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3752 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3753 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3754 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3755 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3756 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3758 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3759 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3761 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3762 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3763 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3764 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3765 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3766 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3767 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3768 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3770 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3771 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3772 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3773 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3774 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3775 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3776 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3777 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3779 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3780 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3781 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3782 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3783 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3784 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3786 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3787 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3788 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3789 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3790 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3791 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3792 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3794 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3795 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3796 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3797 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3798 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3799 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3800 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3802 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3803 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3804 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3805 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3806 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3807 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3808 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3810 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3811 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3812 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3813 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3814 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3815 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3816 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3818 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3819 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3820 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3821 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3822 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3823 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3824 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3826 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3827 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3828 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3829 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3830 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3831 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3832 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3834 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3835 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3836 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3837 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3838 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3839 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3840 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3842 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3843 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3844 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3845 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3847 { "OutBound2", NULL, "OB23 Bypass Mux" },
3848 { "OutBound3", NULL, "OB23 Bypass Mux" },
3876 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3877 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3878 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3879 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3880 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3881 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3882 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3883 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3885 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3886 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3887 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3888 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3889 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3890 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3891 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3892 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3894 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3895 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3896 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3897 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3898 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3899 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3900 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3901 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3903 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3904 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3905 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3906 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3907 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3908 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3909 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3910 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3912 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3913 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3914 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3915 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3916 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3917 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3918 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3919 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3921 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3922 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3923 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3924 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3925 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3926 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3927 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3928 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3930 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3931 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3932 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3933 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3934 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3935 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3936 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3937 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3939 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3940 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3941 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3942 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3943 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3944 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3945 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3946 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3948 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3949 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3950 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3951 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3952 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3953 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3954 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3955 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3974 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3975 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3976 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3977 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3978 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3979 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3980 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3981 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3983 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3984 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3985 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3986 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3987 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3988 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3989 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3990 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3992 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3993 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3994 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3995 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3996 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3997 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3998 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3999 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
4001 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
4002 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
4003 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
4004 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
4005 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
4006 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
4007 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
4008 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
4010 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
4011 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
4012 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
4013 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
4014 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
4015 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
4016 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
4017 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
4019 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
4020 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
4021 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
4022 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
4023 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
4024 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
4025 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
4026 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
4028 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
4029 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
4030 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
4031 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
4032 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
4033 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
4034 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
4035 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
4037 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
4038 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
4039 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
4040 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
4041 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
4042 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
4043 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
4044 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
4046 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
4047 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
4048 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
4049 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
4050 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
4051 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
4052 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
4053 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
4093 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
4094 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
4095 { "ADDA1 Mux", "OB 67", "OB67" },
4097 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
4098 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
4099 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
4100 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
4101 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
4102 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
4104 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
4105 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
4106 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
4107 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
4112 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
4113 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
4114 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
4115 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
4116 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
4117 { "DAC2 L Mux", "OB 2", "OutBound2" },
4119 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
4120 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
4121 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
4122 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
4123 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
4124 { "DAC2 R Mux", "OB 3", "OutBound3" },
4125 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
4126 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
4128 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
4129 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
4130 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
4131 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
4132 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
4133 { "DAC3 L Mux", "OB 4", "OutBound4" },
4135 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
4136 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
4137 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
4138 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
4139 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
4140 { "DAC3 R Mux", "OB 5", "OutBound5" },
4142 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
4143 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
4144 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
4145 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
4146 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
4147 { "DAC4 L Mux", "OB 6", "OutBound6" },
4149 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
4150 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
4151 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
4152 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
4153 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
4154 { "DAC4 R Mux", "OB 7", "OutBound7" },
4156 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
4157 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
4158 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
4159 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
4160 { "Sidetone Mux", "ADC1", "ADC 1" },
4161 { "Sidetone Mux", "ADC2", "ADC 2" },
4162 { "Sidetone Mux", NULL, "Sidetone Power" },
4164 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
4166 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
4169 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
4171 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4176 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
4178 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
4179 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
4182 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
4184 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
4185 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
4191 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
4192 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
4197 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4198 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4204 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4205 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4210 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4211 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4224 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4225 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4226 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4227 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4229 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4230 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4231 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4232 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4234 { "DAC 1", NULL, "DAC12 SRC Mux" },
4235 { "DAC 2", NULL, "DAC12 SRC Mux" },
4236 { "DAC 3", NULL, "DAC3 SRC Mux" },
4238 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4239 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4240 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4241 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4242 { "PDM1 L Mux", NULL, "PDM1 Power" },
4243 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4244 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4245 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4246 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4247 { "PDM1 R Mux", NULL, "PDM1 Power" },
4248 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4249 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4250 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4251 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4252 { "PDM2 L Mux", NULL, "PDM2 Power" },
4253 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4254 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4255 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4256 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4257 { "PDM2 R Mux", NULL, "PDM2 Power" },
4271 { "PDM1L", NULL, "PDM1 L Mux" },
4272 { "PDM1R", NULL, "PDM1 R Mux" },
4273 { "PDM2L", NULL, "PDM2 L Mux" },
4274 { "PDM2R", NULL, "PDM2 R Mux" },
4290 struct snd_soc_component *component = dai->component; in rt5677_hw_params()
4295 rt5677->lrck[dai->id] = params_rate(params); in rt5677_hw_params()
4296 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4298 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", in rt5677_hw_params()
4299 rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4300 return -EINVAL; in rt5677_hw_params()
4304 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5677_hw_params()
4305 return -EINVAL; in rt5677_hw_params()
4308 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); in rt5677_hw_params()
4310 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt5677_hw_params()
4311 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); in rt5677_hw_params()
4312 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt5677_hw_params()
4313 bclk_ms, pre_div, dai->id); in rt5677_hw_params()
4328 return -EINVAL; in rt5677_hw_params()
4331 switch (dai->id) { in rt5677_hw_params()
4335 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_hw_params()
4337 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4343 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_hw_params()
4345 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4352 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_hw_params()
4354 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4361 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_hw_params()
4363 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4375 struct snd_soc_component *component = dai->component; in rt5677_set_dai_fmt()
4381 rt5677->master[dai->id] = 1; in rt5677_set_dai_fmt()
4385 rt5677->master[dai->id] = 0; in rt5677_set_dai_fmt()
4388 return -EINVAL; in rt5677_set_dai_fmt()
4398 return -EINVAL; in rt5677_set_dai_fmt()
4414 return -EINVAL; in rt5677_set_dai_fmt()
4417 switch (dai->id) { in rt5677_set_dai_fmt()
4419 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_set_dai_fmt()
4424 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_set_dai_fmt()
4429 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_set_dai_fmt()
4434 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_set_dai_fmt()
4449 struct snd_soc_component *component = dai->component; in rt5677_set_dai_sysclk()
4453 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) in rt5677_set_dai_sysclk()
4467 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5677_set_dai_sysclk()
4468 return -EINVAL; in rt5677_set_dai_sysclk()
4470 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_sysclk()
4472 rt5677->sysclk = freq; in rt5677_set_dai_sysclk()
4473 rt5677->sysclk_src = clk_id; in rt5677_set_dai_sysclk()
4475 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5677_set_dai_sysclk()
4481 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4494 return -EINVAL; in rt5677_pll_calc()
4502 struct snd_soc_component *component = dai->component; in rt5677_set_dai_pll()
4507 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && in rt5677_set_dai_pll()
4508 freq_out == rt5677->pll_out) in rt5677_set_dai_pll()
4512 dev_dbg(component->dev, "PLL disabled\n"); in rt5677_set_dai_pll()
4514 rt5677->pll_in = 0; in rt5677_set_dai_pll()
4515 rt5677->pll_out = 0; in rt5677_set_dai_pll()
4516 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4523 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4530 switch (dai->id) { in rt5677_set_dai_pll()
4532 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4536 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4540 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4544 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4552 dev_err(component->dev, "Unknown PLL source %d\n", source); in rt5677_set_dai_pll()
4553 return -EINVAL; in rt5677_set_dai_pll()
4558 dev_err(component->dev, "Unsupported input clock %d\n", freq_in); in rt5677_set_dai_pll()
4562 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", in rt5677_set_dai_pll()
4566 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, in rt5677_set_dai_pll()
4568 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, in rt5677_set_dai_pll()
4572 rt5677->pll_in = freq_in; in rt5677_set_dai_pll()
4573 rt5677->pll_out = freq_out; in rt5677_set_dai_pll()
4574 rt5677->pll_src = source; in rt5677_set_dai_pll()
4582 struct snd_soc_component *component = dai->component; in rt5677_set_tdm_slot()
4622 switch (dai->id) { in rt5677_set_tdm_slot()
4624 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4626 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, in rt5677_set_tdm_slot()
4630 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4632 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, in rt5677_set_tdm_slot()
4656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4660 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4669 rt5677->is_vref_slow = false; in rt5677_set_bias_level()
4670 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4672 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_set_bias_level()
4679 rt5677->dsp_vad_en_request) { in rt5677_set_bias_level()
4680 /* Re-enable the DSP if it was turned off at suspend */ in rt5677_set_bias_level()
4681 rt5677->dsp_vad_en = true; in rt5677_set_bias_level()
4683 schedule_delayed_work(&rt5677->dsp_work, in rt5677_set_bias_level()
4689 flush_delayed_work(&rt5677->dsp_work); in rt5677_set_bias_level()
4690 if (rt5677->is_dsp_mode) { in rt5677_set_bias_level()
4692 rt5677->dsp_vad_en = false; in rt5677_set_bias_level()
4693 schedule_delayed_work(&rt5677->dsp_work, 0); in rt5677_set_bias_level()
4694 flush_delayed_work(&rt5677->dsp_work); in rt5677_set_bias_level()
4697 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); in rt5677_set_bias_level()
4698 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); in rt5677_set_bias_level()
4699 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4702 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4704 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4707 if (rt5677->dsp_vad_en) in rt5677_set_bias_level()
4724 return regmap_update_bits(rt5677->regmap, reg, m << shift, v << shift); in rt5677_update_gpio_bits()
4753 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); in rt5677_gpio_get()
4771 * 0 - floating
4772 * 1 - pull down
4773 * 2 - pull up
4782 shift = 2 * (1 - offset); in rt5677_gpio_config()
4783 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4790 shift = 2 * (9 - offset); in rt5677_gpio_config()
4791 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4807 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || in rt5677_to_irq()
4808 (rt5677->pdata.jd1_gpio == 2 && in rt5677_to_irq()
4810 (rt5677->pdata.jd1_gpio == 3 && in rt5677_to_irq()
4813 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || in rt5677_to_irq()
4814 (rt5677->pdata.jd2_gpio == 2 && in rt5677_to_irq()
4816 (rt5677->pdata.jd2_gpio == 3 && in rt5677_to_irq()
4819 } else if ((rt5677->pdata.jd3_gpio == 1 && in rt5677_to_irq()
4821 (rt5677->pdata.jd3_gpio == 2 && in rt5677_to_irq()
4823 (rt5677->pdata.jd3_gpio == 3 && in rt5677_to_irq()
4827 return -ENXIO; in rt5677_to_irq()
4830 return irq_create_mapping(rt5677->domain, irq); in rt5677_to_irq()
4849 rt5677->gpio_chip = rt5677_template_chip; in rt5677_init_gpio()
4850 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; in rt5677_init_gpio()
4851 rt5677->gpio_chip.parent = &i2c->dev; in rt5677_init_gpio()
4852 rt5677->gpio_chip.base = -1; in rt5677_init_gpio()
4854 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); in rt5677_init_gpio()
4856 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); in rt5677_init_gpio()
4863 gpiochip_remove(&rt5677->gpio_chip); in rt5677_free_gpio()
4886 rt5677->component = component; in rt5677_probe()
4888 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_probe()
4900 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_probe()
4902 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, in rt5677_probe()
4906 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); in rt5677_probe()
4908 mutex_init(&rt5677->dsp_cmd_lock); in rt5677_probe()
4909 mutex_init(&rt5677->dsp_pri_lock); in rt5677_probe()
4918 cancel_delayed_work_sync(&rt5677->dsp_work); in rt5677_remove()
4920 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_remove()
4921 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_remove()
4922 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_remove()
4930 if (rt5677->irq) { in rt5677_suspend()
4931 cancel_delayed_work_sync(&rt5677->resume_irq_check); in rt5677_suspend()
4932 disable_irq(rt5677->irq); in rt5677_suspend()
4935 if (!rt5677->dsp_vad_en) { in rt5677_suspend()
4936 regcache_cache_only(rt5677->regmap, true); in rt5677_suspend()
4937 regcache_mark_dirty(rt5677->regmap); in rt5677_suspend()
4939 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_suspend()
4940 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_suspend()
4950 if (!rt5677->dsp_vad_en) { in rt5677_resume()
4951 rt5677->pll_src = 0; in rt5677_resume()
4952 rt5677->pll_in = 0; in rt5677_resume()
4953 rt5677->pll_out = 0; in rt5677_resume()
4954 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); in rt5677_resume()
4955 gpiod_set_value_cansleep(rt5677->reset_pin, 0); in rt5677_resume()
4956 if (rt5677->pow_ldo2 || rt5677->reset_pin) in rt5677_resume()
4959 regcache_cache_only(rt5677->regmap, false); in rt5677_resume()
4960 regcache_sync(rt5677->regmap); in rt5677_resume()
4963 if (rt5677->irq) { in rt5677_resume()
4964 enable_irq(rt5677->irq); in rt5677_resume()
4965 schedule_delayed_work(&rt5677->resume_irq_check, 0); in rt5677_resume()
4980 if (rt5677->is_dsp_mode) { in rt5677_read()
4982 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_read()
4986 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_read()
4991 regmap_read(rt5677->regmap_physical, reg, val); in rt5677_read()
5002 if (rt5677->is_dsp_mode) { in rt5677_write()
5004 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_write()
5009 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_write()
5014 regmap_write(rt5677->regmap_physical, reg, val); in rt5677_write()
5039 .name = "rt5677-aif1",
5058 .name = "rt5677-aif2",
5077 .name = "rt5677-aif3",
5096 .name = "rt5677-aif4",
5115 .name = "rt5677-slimbus",
5134 .name = "rt5677-dspbuffer",
5214 rt5677->pdata.in1_diff = in rt5677_read_device_properties()
5216 device_property_read_bool(dev, "realtek,in1-differential"); in rt5677_read_device_properties()
5218 rt5677->pdata.in2_diff = in rt5677_read_device_properties()
5220 device_property_read_bool(dev, "realtek,in2-differential"); in rt5677_read_device_properties()
5222 rt5677->pdata.lout1_diff = in rt5677_read_device_properties()
5224 device_property_read_bool(dev, "realtek,lout1-differential"); in rt5677_read_device_properties()
5226 rt5677->pdata.lout2_diff = in rt5677_read_device_properties()
5228 device_property_read_bool(dev, "realtek,lout2-differential"); in rt5677_read_device_properties()
5230 rt5677->pdata.lout3_diff = in rt5677_read_device_properties()
5232 device_property_read_bool(dev, "realtek,lout3-differential"); in rt5677_read_device_properties()
5234 device_property_read_u8_array(dev, "realtek,gpio-config", in rt5677_read_device_properties()
5235 rt5677->pdata.gpio_config, in rt5677_read_device_properties()
5240 rt5677->pdata.dmic2_clk_pin = val; in rt5677_read_device_properties()
5243 !device_property_read_u32(dev, "realtek,jd1-gpio", &val)) in rt5677_read_device_properties()
5244 rt5677->pdata.jd1_gpio = val; in rt5677_read_device_properties()
5247 !device_property_read_u32(dev, "realtek,jd2-gpio", &val)) in rt5677_read_device_properties()
5248 rt5677->pdata.jd2_gpio = val; in rt5677_read_device_properties()
5251 !device_property_read_u32(dev, "realtek,jd3-gpio", &val)) in rt5677_read_device_properties()
5252 rt5677->pdata.jd3_gpio = val; in rt5677_read_device_properties()
5283 if (!rt5677->is_dsp_mode) in rt5677_check_hotword()
5286 if (regmap_read(rt5677->regmap, RT5677_GPIO_CTRL1, ®_gpio)) in rt5677_check_hotword()
5294 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_check_hotword()
5307 mutex_lock(&rt5677->irq_lock); in rt5677_irq()
5325 ret = regmap_read(rt5677->regmap, RT5677_IRQ_CTRL1, ®_irq); in rt5677_irq()
5327 dev_err(rt5677->dev, "failed reading IRQ status: %d\n", in rt5677_irq()
5336 virq = irq_find_mapping(rt5677->domain, i); in rt5677_irq()
5355 ret = regmap_write(rt5677->regmap, RT5677_IRQ_CTRL1, reg_irq); in rt5677_irq()
5357 dev_err(rt5677->dev, "failed updating IRQ status: %d\n", in rt5677_irq()
5364 mutex_unlock(&rt5677->irq_lock); in rt5677_irq()
5387 * scheduled by soc-jack may run and read wrong jack gpio values, since in rt5677_resume_irq_check()
5393 mutex_lock(&rt5677->irq_lock); in rt5677_resume_irq_check()
5395 if (rt5677->irq_en & rt5677_irq_descs[i].enable_mask) { in rt5677_resume_irq_check()
5396 virq = irq_find_mapping(rt5677->domain, i); in rt5677_resume_irq_check()
5401 mutex_unlock(&rt5677->irq_lock); in rt5677_resume_irq_check()
5408 mutex_lock(&rt5677->irq_lock); in rt5677_irq_bus_lock()
5416 regmap_update_bits(rt5677->regmap, RT5677_IRQ_CTRL1, in rt5677_irq_bus_sync_unlock()
5418 RT5677_EN_IRQ_GPIO_JD3, rt5677->irq_en); in rt5677_irq_bus_sync_unlock()
5419 mutex_unlock(&rt5677->irq_lock); in rt5677_irq_bus_sync_unlock()
5426 rt5677->irq_en |= rt5677_irq_descs[data->hwirq].enable_mask; in rt5677_irq_enable()
5433 rt5677->irq_en &= ~rt5677_irq_descs[data->hwirq].enable_mask; in rt5677_irq_disable()
5447 struct rt5677_priv *rt5677 = h->host_data; in rt5677_irq_map()
5468 if (!rt5677->pdata.jd1_gpio && in rt5677_init_irq()
5469 !rt5677->pdata.jd2_gpio && in rt5677_init_irq()
5470 !rt5677->pdata.jd3_gpio) in rt5677_init_irq()
5473 if (!i2c->irq) { in rt5677_init_irq()
5474 dev_err(&i2c->dev, "No interrupt specified\n"); in rt5677_init_irq()
5475 return -EINVAL; in rt5677_init_irq()
5478 mutex_init(&rt5677->irq_lock); in rt5677_init_irq()
5479 INIT_DELAYED_WORK(&rt5677->resume_irq_check, rt5677_resume_irq_check); in rt5677_init_irq()
5486 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_init_irq()
5490 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL1, 0xff, 0xff); in rt5677_init_irq()
5493 if (rt5677->pdata.jd1_gpio) { in rt5677_init_irq()
5495 jd_val |= rt5677->pdata.jd1_gpio << RT5677_SEL_GPIO_JD1_SFT; in rt5677_init_irq()
5497 if (rt5677->pdata.jd2_gpio) { in rt5677_init_irq()
5499 jd_val |= rt5677->pdata.jd2_gpio << RT5677_SEL_GPIO_JD2_SFT; in rt5677_init_irq()
5501 if (rt5677->pdata.jd3_gpio) { in rt5677_init_irq()
5503 jd_val |= rt5677->pdata.jd3_gpio << RT5677_SEL_GPIO_JD3_SFT; in rt5677_init_irq()
5505 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, jd_mask, jd_val); in rt5677_init_irq()
5508 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, in rt5677_init_irq()
5512 rt5677->domain = irq_domain_create_linear(dev_fwnode(&i2c->dev), in rt5677_init_irq()
5514 if (!rt5677->domain) { in rt5677_init_irq()
5515 dev_err(&i2c->dev, "Failed to create IRQ domain\n"); in rt5677_init_irq()
5516 return -ENOMEM; in rt5677_init_irq()
5519 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5677_irq, in rt5677_init_irq()
5523 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret); in rt5677_init_irq()
5525 rt5677->irq = i2c->irq; in rt5677_init_irq()
5532 struct device *dev = &i2c->dev; in rt5677_i2c_probe()
5537 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), in rt5677_i2c_probe()
5540 return -ENOMEM; in rt5677_i2c_probe()
5542 rt5677->dev = &i2c->dev; in rt5677_i2c_probe()
5543 rt5677->set_dsp_vad = rt5677_set_dsp_vad; in rt5677_i2c_probe()
5544 INIT_DELAYED_WORK(&rt5677->dsp_work, rt5677_dsp_work); in rt5677_i2c_probe()
5547 rt5677->type = (enum rt5677_type)(uintptr_t)device_get_match_data(dev); in rt5677_i2c_probe()
5548 if (rt5677->type == 0) in rt5677_i2c_probe()
5549 return -EINVAL; in rt5677_i2c_probe()
5551 rt5677_read_device_properties(rt5677, &i2c->dev); in rt5677_i2c_probe()
5553 /* pow-ldo2 and reset are optional. The codec pins may be statically in rt5677_i2c_probe()
5557 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5558 "realtek,pow-ldo2", GPIOD_OUT_HIGH); in rt5677_i2c_probe()
5559 if (IS_ERR(rt5677->pow_ldo2)) { in rt5677_i2c_probe()
5560 ret = PTR_ERR(rt5677->pow_ldo2); in rt5677_i2c_probe()
5561 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); in rt5677_i2c_probe()
5564 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5566 if (IS_ERR(rt5677->reset_pin)) { in rt5677_i2c_probe()
5567 ret = PTR_ERR(rt5677->reset_pin); in rt5677_i2c_probe()
5568 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); in rt5677_i2c_probe()
5572 if (rt5677->pow_ldo2 || rt5677->reset_pin) { in rt5677_i2c_probe()
5580 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, in rt5677_i2c_probe()
5582 if (IS_ERR(rt5677->regmap_physical)) { in rt5677_i2c_probe()
5583 ret = PTR_ERR(rt5677->regmap_physical); in rt5677_i2c_probe()
5584 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5589 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); in rt5677_i2c_probe()
5590 if (IS_ERR(rt5677->regmap)) { in rt5677_i2c_probe()
5591 ret = PTR_ERR(rt5677->regmap); in rt5677_i2c_probe()
5592 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5597 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); in rt5677_i2c_probe()
5599 dev_err(&i2c->dev, in rt5677_i2c_probe()
5601 return -ENODEV; in rt5677_i2c_probe()
5604 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_i2c_probe()
5606 ret = regmap_register_patch(rt5677->regmap, init_list, in rt5677_i2c_probe()
5609 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); in rt5677_i2c_probe()
5611 if (rt5677->pdata.in1_diff) in rt5677_i2c_probe()
5612 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5615 if (rt5677->pdata.in2_diff) in rt5677_i2c_probe()
5616 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5619 if (rt5677->pdata.lout1_diff) in rt5677_i2c_probe()
5620 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5623 if (rt5677->pdata.lout2_diff) in rt5677_i2c_probe()
5624 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5627 if (rt5677->pdata.lout3_diff) in rt5677_i2c_probe()
5628 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5631 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_i2c_probe()
5632 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, in rt5677_i2c_probe()
5640 if (rt5677->pdata.micbias1_vdd_3v3) in rt5677_i2c_probe()
5641 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, in rt5677_i2c_probe()
5648 dev_err(&i2c->dev, "Failed to initialize irq: %d\n", ret); in rt5677_i2c_probe()
5650 return devm_snd_soc_register_component(&i2c->dev, in rt5677_i2c_probe()