Lines Matching +full:0 +full:xc400
33 #define RT298_VENDOR_ID 0x10ec0298
50 { 0x01, 0xa5a8 },
51 { 0x02, 0x8e95 },
52 { 0x03, 0x0002 },
53 { 0x04, 0xaf67 },
54 { 0x08, 0x200f },
55 { 0x09, 0xd010 },
56 { 0x0a, 0x0100 },
57 { 0x0b, 0x0000 },
58 { 0x0d, 0x2800 },
59 { 0x0f, 0x0022 },
60 { 0x19, 0x0217 },
61 { 0x20, 0x0020 },
62 { 0x33, 0x0208 },
63 { 0x46, 0x0300 },
64 { 0x49, 0x4004 },
65 { 0x4f, 0x50c9 },
66 { 0x50, 0x3000 },
67 { 0x63, 0x1b02 },
68 { 0x67, 0x1111 },
69 { 0x68, 0x1016 },
70 { 0x69, 0x273f },
75 { 0x00170500, 0x00000400 },
76 { 0x00220000, 0x00000031 },
77 { 0x00239000, 0x0000007f },
78 { 0x0023a000, 0x0000007f },
79 { 0x00270500, 0x00000400 },
80 { 0x00370500, 0x00000400 },
81 { 0x00870500, 0x00000400 },
82 { 0x00920000, 0x00000031 },
83 { 0x00935000, 0x000000c3 },
84 { 0x00936000, 0x000000c3 },
85 { 0x00970500, 0x00000400 },
86 { 0x00b37000, 0x00000097 },
87 { 0x00b37200, 0x00000097 },
88 { 0x00b37300, 0x00000097 },
89 { 0x00c37000, 0x00000000 },
90 { 0x00c37100, 0x00000080 },
91 { 0x01270500, 0x00000400 },
92 { 0x01370500, 0x00000400 },
93 { 0x01371f00, 0x411111f0 },
94 { 0x01439000, 0x00000080 },
95 { 0x0143a000, 0x00000080 },
96 { 0x01470700, 0x00000000 },
97 { 0x01470500, 0x00000400 },
98 { 0x01470c00, 0x00000000 },
99 { 0x01470100, 0x00000000 },
100 { 0x01837000, 0x00000000 },
101 { 0x01870500, 0x00000400 },
102 { 0x02050000, 0x00000000 },
103 { 0x02139000, 0x00000080 },
104 { 0x0213a000, 0x00000080 },
105 { 0x02170100, 0x00000000 },
106 { 0x02170500, 0x00000400 },
107 { 0x02170700, 0x00000000 },
108 { 0x02270100, 0x00000000 },
109 { 0x02370100, 0x00000000 },
110 { 0x01870700, 0x00000020 },
111 { 0x00830000, 0x000000c3 },
112 { 0x00930000, 0x000000c3 },
113 { 0x01270700, 0x00000000 },
119 case 0 ... 0xff: in rt298_volatile_register()
124 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): in rt298_volatile_register()
125 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): in rt298_volatile_register()
126 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): in rt298_volatile_register()
138 case 0 ... 0xff: in rt298_readable_register()
184 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0): in rt298_readable_register()
185 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0): in rt298_readable_register()
186 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0): in rt298_readable_register()
199 for (i = 0; i < INDEX_CACHE_SIZE; i++) { in rt298_index_sync()
234 *hp = buf & 0x80000000; in rt298_jack_detect()
241 RT298_DC_GAIN, 0x200, 0x200); in rt298_jack_detect()
250 RT298_POWER_CTRL1, 0x1001, 0); in rt298_jack_detect()
252 RT298_POWER_CTRL2, 0x4, 0x4); in rt298_jack_detect()
254 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24); in rt298_jack_detect()
258 RT298_CBJ_CTRL1, 0xfcc0, 0xd400); in rt298_jack_detect()
262 if (0x0070 == (val & 0x0070)) { in rt298_jack_detect()
266 RT298_CBJ_CTRL1, 0xfcc0, 0xe400); in rt298_jack_detect()
270 if (0x0070 == (val & 0x0070)) { in rt298_jack_detect()
276 0xfcc0, 0xc400); in rt298_jack_detect()
281 RT298_DC_GAIN, 0x200, 0x0); in rt298_jack_detect()
285 regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20); in rt298_jack_detect()
287 RT298_CBJ_CTRL1, 0x0400, 0x0000); in rt298_jack_detect()
291 *hp = buf & 0x80000000; in rt298_jack_detect()
293 *mic = buf & 0x80000000; in rt298_jack_detect()
305 return 0; in rt298_jack_detect()
312 int status = 0; in rt298_jack_detect_work()
316 if (rt298_jack_detect(rt298, &hp, &mic) < 0) in rt298_jack_detect_work()
345 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x2); in rt298_mic_detect()
351 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x2, 0x0); in rt298_mic_detect()
358 return 0; in rt298_mic_detect()
370 return 0; in is_mclk_mode()
373 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
374 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
378 RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
380 RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
382 0, 0x3, 0, mic_vol_tlv),
409 RT298_SET_PIN_SFT, 1, 0);
425 0, 4, 5,
433 SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum);
447 0, rt298_dac_src);
454 0, rt298_dac_src);
475 return 0; in rt298_spk_event()
478 return 0; in rt298_spk_event()
488 snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0x20); in rt298_set_dmic1_event()
491 snd_soc_component_write(component, RT298_SET_PIN_DMIC1, 0); in rt298_set_dmic1_event()
494 return 0; in rt298_set_dmic1_event()
497 return 0; in rt298_set_dmic1_event()
506 nid = (w->reg >> 20) & 0xff; in rt298_adc_event()
511 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), in rt298_adc_event()
512 0x7080, 0x7000); in rt298_adc_event()
514 if (!(snd_soc_component_read(component, RT298_VAD_CTRL) & 0x200)) { in rt298_adc_event()
519 RT298_D_FILTER_CTRL, 0x2, 0x2); in rt298_adc_event()
522 RT298_D_FILTER_CTRL, 0x2, 0x0); in rt298_adc_event()
526 RT298_D_FILTER_CTRL, 0x4, 0x4); in rt298_adc_event()
529 RT298_D_FILTER_CTRL, 0x4, 0x0); in rt298_adc_event()
536 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0), in rt298_adc_event()
537 0x7080, 0x7080); in rt298_adc_event()
540 return 0; in rt298_adc_event()
543 return 0; in rt298_adc_event()
554 RT298_A_BIAS_CTRL3, 0xc000, 0x8000); in rt298_mic1_event()
556 RT298_A_BIAS_CTRL2, 0xc000, 0x8000); in rt298_mic1_event()
560 RT298_A_BIAS_CTRL3, 0xc000, 0x0000); in rt298_mic1_event()
562 RT298_A_BIAS_CTRL2, 0xc000, 0x0000); in rt298_mic1_event()
565 return 0; in rt298_mic1_event()
568 return 0; in rt298_mic1_event()
574 12, 1, NULL, 0),
576 0, 1, NULL, 0),
578 1, 0, NULL, 0),
580 2, 0, NULL, 0),
582 3, 0, NULL, 0),
584 4, 1, NULL, 0),
586 13, 1, NULL, 0),
590 5, 0, NULL, 0),
592 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU |
603 SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1,
604 NULL, 0, rt298_set_dmic1_event,
606 SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1,
607 NULL, 0),
609 0, 0, NULL, 0),
612 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
616 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
617 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
620 SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1,
623 SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1,
628 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
629 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
630 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
631 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
635 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
636 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
639 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux),
640 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux),
643 RT298_SET_PIN_SFT, 0, NULL, 0),
646 SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1,
648 SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1,
649 NULL, 0),
652 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
655 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
657 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
669 {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
706 {"ADC 0 Mux", "Dmic", "DMIC1"},
707 {"ADC 0 Mux", "RECMIX", "RECMIX"},
708 {"ADC 0 Mux", "Mic", "MIC1"},
713 {"ADC 0", NULL, "ADC 0 Mux"},
716 {"AIF1TX", NULL, "ADC 0"},
719 {"DAC 0", NULL, "AIF1RX"},
722 {"Front", "DAC Switch", "DAC 0"},
751 unsigned int val = 0; in rt298_hw_params()
755 /* bit 14 0:48K 1:44.1K */ in rt298_hw_params()
784 /* bit 3:0 Number of Channel */ in rt298_hw_params()
792 d_len_code = 0; in rt298_hw_params()
796 d_len_code = 0; in rt298_hw_params()
797 val |= (0x1 << 4); in rt298_hw_params()
801 val |= (0x4 << 4); in rt298_hw_params()
805 val |= (0x2 << 4); in rt298_hw_params()
809 val |= (0x3 << 4); in rt298_hw_params()
819 RT298_I2S_CTRL1, 0x0018, d_len_code << 3); in rt298_hw_params()
820 dev_dbg(component->dev, "format val = 0x%x\n", val); in rt298_hw_params()
822 snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x407f, val); in rt298_hw_params()
823 snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x407f, val); in rt298_hw_params()
825 return 0; in rt298_hw_params()
835 RT298_I2S_CTRL1, 0x800, 0x800); in rt298_set_dai_fmt()
839 RT298_I2S_CTRL1, 0x800, 0x0); in rt298_set_dai_fmt()
848 RT298_I2S_CTRL1, 0x300, 0x0); in rt298_set_dai_fmt()
852 RT298_I2S_CTRL1, 0x300, 0x1 << 8); in rt298_set_dai_fmt()
856 RT298_I2S_CTRL1, 0x300, 0x2 << 8); in rt298_set_dai_fmt()
860 RT298_I2S_CTRL1, 0x300, 0x3 << 8); in rt298_set_dai_fmt()
865 /* bit 15 Stream Type 0:PCM 1:Non-PCM */ in rt298_set_dai_fmt()
866 snd_soc_component_update_bits(component, RT298_DAC_FORMAT, 0x8000, 0); in rt298_set_dai_fmt()
867 snd_soc_component_update_bits(component, RT298_ADC_FORMAT, 0x8000, 0); in rt298_set_dai_fmt()
869 return 0; in rt298_set_dai_fmt()
882 RT298_I2S_CTRL2, 0x0100, 0x0); in rt298_set_dai_sysclk()
884 RT298_PLL_CTRL1, 0x20, 0x20); in rt298_set_dai_sysclk()
887 RT298_I2S_CTRL2, 0x0100, 0x0100); in rt298_set_dai_sysclk()
889 RT298_PLL_CTRL1, 0x20, 0x0); in rt298_set_dai_sysclk()
899 RT298_I2S_CTRL2, 0x40, 0x40); in rt298_set_dai_sysclk()
907 RT298_I2S_CTRL2, 0x40, 0x0); in rt298_set_dai_sysclk()
912 RT298_I2S_CTRL2, 0x8, 0x0); in rt298_set_dai_sysclk()
914 RT298_CLK_DIV, 0xfc1e, 0x0004); in rt298_set_dai_sysclk()
919 RT298_I2S_CTRL2, 0x8, 0x8); in rt298_set_dai_sysclk()
921 RT298_CLK_DIV, 0xfc1e, 0x5406); in rt298_set_dai_sysclk()
931 return 0; in rt298_set_dai_sysclk()
941 RT298_I2S_CTRL1, 0x1000, 0x1000); in rt298_set_bclk_ratio()
944 RT298_I2S_CTRL1, 0x1000, 0x0); in rt298_set_bclk_ratio()
947 return 0; in rt298_set_bclk_ratio()
959 snd_soc_component_update_bits(component, 0x0d, 0x200, 0x200); in rt298_set_bias_level()
960 snd_soc_component_update_bits(component, 0x52, 0x80, 0x0); in rt298_set_bias_level()
962 snd_soc_component_update_bits(component, 0x0d, 0x200, 0x0); in rt298_set_bias_level()
963 snd_soc_component_update_bits(component, 0x52, 0x80, 0x80); in rt298_set_bias_level()
976 return 0; in rt298_set_bias_level()
984 int ret, status = 0; in rt298_irq()
989 regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1); in rt298_irq()
991 if (ret == 0) { in rt298_irq()
1017 return 0; in rt298_probe()
1037 return 0; in rt298_suspend()
1048 return 0; in rt298_resume()
1130 .max_register = 0x02370100,
1141 {"rt298", 0},
1148 { "INT343A", 0 },
1218 for (i = 0; i < INDEX_CACHE_SIZE; i++) in rt298_i2c_probe()
1221 for (i = 0; i < ARRAY_SIZE(rt298_reg); i++) in rt298_i2c_probe()
1241 regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80); in rt298_i2c_probe()
1242 regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860); in rt298_i2c_probe()
1244 regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20); in rt298_i2c_probe()
1248 for (i = 0; i < RT298_POWER_REG_LEN; i++) in rt298_i2c_probe()
1254 regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000); in rt298_i2c_probe()
1255 regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816); in rt298_i2c_probe()
1257 RT298_CBJ_CTRL1, 0xf000, 0xb000); in rt298_i2c_probe()
1260 RT298_CBJ_CTRL1, 0xf000, 0x5000); in rt298_i2c_probe()
1266 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40); in rt298_i2c_probe()
1268 regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0); in rt298_i2c_probe()
1272 regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000); in rt298_i2c_probe()
1274 RT298_WIND_FILTER_CTRL, 0x0082, 0x0082); in rt298_i2c_probe()
1276 regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81); in rt298_i2c_probe()
1277 regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82); in rt298_i2c_probe()
1278 regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84); in rt298_i2c_probe()
1279 regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2); in rt298_i2c_probe()
1286 if (ret != 0) { in rt298_i2c_probe()