Lines Matching +full:fll1 +full:- +full:clk

1 /* SPDX-License-Identifier: GPL-2.0-only */
95 /* 16-bit control register address, and 16-bits control register data */
123 /* FLL1 (0x04) */
159 /* 0 - open, 1 - short to GND */
172 #define NAU8825_JACK_POLARITY	(1 << 1) /* 0 - active low, 1 - active high */
239 #define NAU8825_JKDET_PULL_UP	(1 << 11) /* 0 - pull down, 1 - pull up */
240 #define NAU8825_JKDET_PULL_EN	(1 << 9) /* 0 - enable pull, 1 - disable */
241 #define NAU8825_JKDET_OUTPUT_EN	(1 << 8) /* 0 - enable input, 1 - enable output */
273 #define NAU8825_I2S_TRISTATE	(1 << 15) /* 0 - normal mode, 1 - Hi-Z output */
500 	struct clk *mclk;
505 	int mclk_freq; /* 0 - mclk is disabled */