Lines Matching +full:3 +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * max98925.h -- MAX98925 ALSA SoC Audio driver
5 * Copyright 2013-2015 Maxim Integrated Products
78 #define M98925_THERMWARN_STATUS_MASK (1<<3)
79 #define M98925_THERMWARN_STATUS_SHIFT 3
86 #define M98925_SPKCURNT_STATUS_MASK (1<<5)
87 #define M98925_SPKCURNT_STATUS_SHIFT 5
92 #define M98925_ALCINFH_STATUS_MASK (1<<3)
93 #define M98925_ALCINFH_STATUS_SHIFT 3
109 #define M98925_INVALSLOT_STATUS_MASK (1<<5)
110 #define M98925_INVALSLOT_STATUS_SHIFT 5
115 #define M98925_VBSTOVFL_STATUS_MASK (1<<3)
116 #define M98925_VBSTOVFL_STATUS_SHIFT 3
129 #define M98925_THERMWARN_END_STATE_MASK (1<<3)
130 #define M98925_THERMWARN_END_STATE_SHIFT 3
143 #define M98925_SPRCURNT_STATE_MASK (1<<5)
144 #define M98925_SPRCURNT_STATE_SHIFT 5
149 #define M98925_ALCINFH_STATE_MASK (1<<3)
150 #define M98925_ALCINFH_STATE_SHIFT 3
166 #define M98925_INVALSLOT_STATE_MASK (1<<5)
167 #define M98925_INVALSLOT_STATE_SHIFT 5
172 #define M98925_VBSTOVFL_STATE_MASK (1<<3)
173 #define M98925_VBSTOVFL_STATE_SHIFT 3
186 #define M98925_THERMWARN_END_FLAG_MASK (1<<3)
187 #define M98925_THERMWARN_END_FLAG_SHIFT 3
200 #define M98925_SPKCURNT_FLAG_MASK (1<<5)
201 #define M98925_SPKCURNT_FLAG_SHIFT 5
206 #define M98925_ALCINFH_FLAG_MASK (1<<3)
207 #define M98925_ALCINFH_FLAG_SHIFT 3
223 #define M98925_INVALSLOT_FLAG_MASK (1<<5)
224 #define M98925_INVALSLOT_FLAG_SHIFT 5
229 #define M98925_VBSTOVFL_FLAG_MASK (1<<3)
230 #define M98925_VBSTOVFL_FLAG_SHIFT 3
243 #define M98925_THERMWARN_END_EN_MASK (1<<3)
244 #define M98925_THERMWARN_END_EN_SHIFT 3
257 #define M98925_SPKCURNT_EN_MASK (1<<5)
258 #define M98925_SPKCURNT_EN_SHIFT 5
263 #define M98925_ALCINFH_EN_MASK (1<<3)
264 #define M98925_ALCINFH_EN_SHIFT 3
280 #define M98925_INVALSLOT_EN_MASK (1<<5)
281 #define M98925_INVALSLOT_EN_SHIFT 5
286 #define M98925_VBSTOVFL_EN_MASK (1<<3)
287 #define M98925_VBSTOVFL_EN_SHIFT 3
300 #define M98925_THERMWARN_END_CLR_MASK (1<<3)
301 #define M98925_THERMWARN_END_CLR_SHIFT 3
314 #define M98925_SPKCURNT_CLR_MASK (1<<5)
315 #define M98925_SPKCURNT_CLR_SHIFT 5
320 #define M98925_ALCINFH_CLR_MASK (1<<3)
321 #define M98925_ALCINFH_CLR_SHIFT 3
337 #define M98925_INVALSLOT_CLR_MASK (1<<5)
338 #define M98925_INVALSLOT_CLR_SHIFT 5
343 #define M98925_VBSTOVFL_CLR_MASK (1<<3)
344 #define M98925_VBSTOVFL_CLR_SHIFT 3
362 #define M98925_ER_THERMWARN_MAP_WIDTH 3
370 #define M98925_ER_ALCMUT_MAP_WIDTH 3
371 #define M98925_ER_ALCP_EN_MASK (1<<3)
372 #define M98925_ER_ALCP_EN_SHIFT 3
376 #define M98925_ER_ALCP_MAP_WIDTH 3
384 #define M98925_ER_ALCINFH_MAP_WIDTH 3
385 #define M98925_ER_ALCACT_EN_MASK (1<<3)
386 #define M98925_ER_ALCACT_EN_SHIFT 3
390 #define M98925_ER_ALCACT_MAP_WIDTH 3
398 #define M98925_ER_SPKCURNT_MAP_WIDTH 3
409 #define M98925_ER_IMONOVFL_MAP_WIDTH 3
410 #define M98925_ER_VMONOVFL_EN_MASK (1<<3)
411 #define M98925_ER_VMONOVFL_EN_SHIFT 3
415 #define M98925_ER_VMONOVFL_MAP_WIDTH 3
423 #define M98925_ER_VBSTOVFL_MAP_WIDTH 3
424 #define M98925_ER_VBATOVFL_EN_MASK (1<<3)
425 #define M98925_ER_VBATOVFL_EN_SHIFT 3
429 #define M98925_ER_VBATOVFL_MAP_WIDTH 3
437 #define M98925_ER_INVALSLOT_MAP_WIDTH 3
438 #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3)
439 #define M98925_ER_SLOTCNFLT_EN_SHIFT 3
443 #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3
446 #define M98925_ER_SLOTOVRN_EN_MASK (1<<3)
447 #define M98925_ER_SLOTOVRN_EN_SHIFT 3
451 #define M98925_ER_SLOTOVRN_MAP_WIDTH 3
468 #define M98925_DAI_MAS_MASK (1<<3)
469 #define M98925_DAI_MAS_SHIFT 3
473 #define M98925_DAI_BSEL_WIDTH 3
507 #define M98925_DAI_WCI_MASK (1<<3)
508 #define M98925_DAI_WCI_SHIFT 3
522 #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT)
531 #define M98925_DAI_INR_SOURCE_MASK (0x07<<3)
532 #define M98925_DAI_INR_SOURCE_SHIFT 3
533 #define M98925_DAI_INR_SOURCE_WIDTH 3
536 #define M98925_DAI_INL_SOURCE_WIDTH 3
539 #define M98925_DAI_VMON_EN_MASK (1<<5)
540 #define M98925_DAI_VMON_EN_SHIFT 5
544 #define M98925_DAI_VMON_SLOT_WIDTH 5
549 #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT)
551 #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT)
579 #define M98925_DAI_IMON_EN_MASK (1<<5)
580 #define M98925_DAI_IMON_EN_SHIFT 5
584 #define M98925_DAI_IMON_SLOT_WIDTH 5
589 #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT)
591 #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT)
619 #define M98925_DAI_VBAT_EN_MASK (1<<5)
620 #define M98925_DAI_VBAT_EN_SHIFT 5
624 #define M98925_DAI_VBAT_SLOT_WIDTH 5
627 #define M98925_DAI_VBST_EN_MASK (1<<5)
628 #define M98925_DAI_VBST_EN_SHIFT 5
632 #define M98925_DAI_VBST_SLOT_WIDTH 5
635 #define M98925_DAI_FLAG_EN_MASK (1<<5)
636 #define M98925_DAI_FLAG_EN_SHIFT 5
640 #define M98925_DAI_FLAG_SLOT_WIDTH 5
677 #define M98925_DAC_FILTER_MODE_MASK (1<<3)
678 #define M98925_DAC_FILTER_MODE_SHIFT 3
682 #define M98925_DAC_HPF_WIDTH 3
686 #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT)
688 #define M98925_DAC_HPF_EN_800 (5 << M98925_DAC_HPF_SHIFT)
691 #define M98925_DAC_IN_SEL_MASK (0x03<<5)
692 #define M98925_DAC_IN_SEL_SHIFT 5
696 #define M98925_SPK_GAIN_WIDTH 5
701 #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT)
717 #define M98925_ALC_EN_MASK (1<<5)
718 #define M98925_ALC_EN_SHIFT 5
722 #define M98925_ALC_TH_WIDTH 5
730 #define M98925_ALC_ATK_RATE_WIDTH 3
738 #define M98925_ALC_RLS_RATE_WIDTH 3
751 #define M98925_ALC_MUTE_DLY_WIDTH 3
754 #define M98925_ALC_RLS_DBT_WIDTH 3
774 #define M98925_CLKMON_EN_MASK (1<<5)
775 #define M98925_CLKMON_EN_SHIFT 5
780 #define M98925_ADC_VBST_EN_MASK (1<<3)
781 #define M98925_ADC_VBST_EN_SHIFT 3
810 #define M98925_BST_ILIM_MASK (0x1F<<3)
811 #define M98925_BST_ILIM_SHIFT 3
812 #define M98925_BST_ILIM_WIDTH 5