Lines Matching +full:functional +full:- +full:system +full:- +full:alpine
2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
103 * per-board-type information, used for enumerating and abstracting
104 * chip-specific information
108 * is required at runtime. Maybe separate into an init-only and
109 * a run-time table?
114 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
204 .name = "CL Alpine",
262 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
375 /*--- Interface used by the world ------------------------------------------*/
379 /*--- Internal routines ----------------------------------------------------*/
423 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB; in is_laguna()
428 /*--- Open /dev/fbx ---------------------------------------------------------*/
432 switch_monitor(info->par, 1); in cirrusfb_open()
436 /*--- Close /dev/fbx --------------------------------------------------------*/
439 if (--opencount == 0) in cirrusfb_release()
440 switch_monitor(info->par, 0); in cirrusfb_release()
451 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_mclk()
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
456 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk); in cirrusfb_check_mclk()
462 if (abs(freq - mclk) < 250) { in cirrusfb_check_mclk()
463 dev_dbg(info->device, "Using VCLK = MCLK\n"); in cirrusfb_check_mclk()
465 } else if (abs(freq - (mclk / 2)) < 250) { in cirrusfb_check_mclk()
466 dev_dbg(info->device, "Using VCLK = MCLK/2\n"); in cirrusfb_check_mclk()
478 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_pixclock()
479 unsigned maxclockidx = var->bits_per_pixel >> 3; in cirrusfb_check_pixclock()
482 freq = PICOS2KHZ(var->pixclock ? : 1); in cirrusfb_check_pixclock()
484 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; in cirrusfb_check_pixclock()
485 cinfo->multiplexing = 0; in cirrusfb_check_pixclock()
490 var->pixclock = KHZ2PICOS(maxclock); in cirrusfb_check_pixclock()
492 while ((freq = PICOS2KHZ(var->pixclock)) > maxclock) in cirrusfb_check_pixclock()
493 var->pixclock++; in cirrusfb_check_pixclock()
495 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq); in cirrusfb_check_pixclock()
501 if (var->bits_per_pixel == 8) { in cirrusfb_check_pixclock()
502 switch (cinfo->btype) { in cirrusfb_check_pixclock()
507 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
511 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
521 cinfo->doubleVCLK = 0; in cirrusfb_check_pixclock()
522 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ && in cirrusfb_check_pixclock()
523 var->bits_per_pixel == 16) { in cirrusfb_check_pixclock()
524 cinfo->doubleVCLK = 1; in cirrusfb_check_pixclock()
536 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_var()
538 switch (var->bits_per_pixel) { in cirrusfb_check_var()
540 var->red.offset = 0; in cirrusfb_check_var()
541 var->red.length = 1; in cirrusfb_check_var()
542 var->green = var->red; in cirrusfb_check_var()
543 var->blue = var->red; in cirrusfb_check_var()
547 var->red.offset = 0; in cirrusfb_check_var()
548 var->red.length = 8; in cirrusfb_check_var()
549 var->green = var->red; in cirrusfb_check_var()
550 var->blue = var->red; in cirrusfb_check_var()
554 var->red.offset = 11; in cirrusfb_check_var()
555 var->green.offset = 5; in cirrusfb_check_var()
556 var->blue.offset = 0; in cirrusfb_check_var()
557 var->red.length = 5; in cirrusfb_check_var()
558 var->green.length = 6; in cirrusfb_check_var()
559 var->blue.length = 5; in cirrusfb_check_var()
563 var->red.offset = 16; in cirrusfb_check_var()
564 var->green.offset = 8; in cirrusfb_check_var()
565 var->blue.offset = 0; in cirrusfb_check_var()
566 var->red.length = 8; in cirrusfb_check_var()
567 var->green.length = 8; in cirrusfb_check_var()
568 var->blue.length = 8; in cirrusfb_check_var()
572 dev_dbg(info->device, in cirrusfb_check_var()
573 "Unsupported bpp size: %d\n", var->bits_per_pixel); in cirrusfb_check_var()
574 return -EINVAL; in cirrusfb_check_var()
577 pixels = info->screen_size * 8 / var->bits_per_pixel; in cirrusfb_check_var()
578 if (var->xres_virtual < var->xres) in cirrusfb_check_var()
579 var->xres_virtual = var->xres; in cirrusfb_check_var()
581 if (var->yres_virtual == -1) { in cirrusfb_check_var()
582 var->yres_virtual = pixels / var->xres_virtual; in cirrusfb_check_var()
584 dev_info(info->device, in cirrusfb_check_var()
586 var->xres_virtual, var->yres_virtual); in cirrusfb_check_var()
588 if (var->yres_virtual < var->yres) in cirrusfb_check_var()
589 var->yres_virtual = var->yres; in cirrusfb_check_var()
591 if (var->xres_virtual * var->yres_virtual > pixels) { in cirrusfb_check_var()
592 dev_err(info->device, "mode %dx%dx%d rejected... " in cirrusfb_check_var()
594 var->xres_virtual, var->yres_virtual, in cirrusfb_check_var()
595 var->bits_per_pixel); in cirrusfb_check_var()
596 return -EINVAL; in cirrusfb_check_var()
600 if (var->xoffset > var->xres_virtual - var->xres) in cirrusfb_check_var()
601 var->xoffset = var->xres_virtual - var->xres - 1; in cirrusfb_check_var()
602 if (var->yoffset > var->yres_virtual - var->yres) in cirrusfb_check_var()
603 var->yoffset = var->yres_virtual - var->yres - 1; in cirrusfb_check_var()
605 var->red.msb_right = in cirrusfb_check_var()
606 var->green.msb_right = in cirrusfb_check_var()
607 var->blue.msb_right = in cirrusfb_check_var()
608 var->transp.offset = in cirrusfb_check_var()
609 var->transp.length = in cirrusfb_check_var()
610 var->transp.msb_right = 0; in cirrusfb_check_var()
612 yres = var->yres; in cirrusfb_check_var()
613 if (var->vmode & FB_VMODE_DOUBLE) in cirrusfb_check_var()
615 else if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_check_var()
619 dev_err(info->device, "ERROR: VerticalTotal >= 1280; " in cirrusfb_check_var()
621 return -EINVAL; in cirrusfb_check_var()
625 return -EINVAL; in cirrusfb_check_var()
628 var->accel_flags = FB_ACCELF_TEXT; in cirrusfb_check_var()
635 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_mclk_as_source()
639 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
642 dev_dbg(info->device, "Set %s as pixclock source.\n", in cirrusfb_set_mclk_as_source()
645 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
649 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
651 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); in cirrusfb_set_mclk_as_source()
661 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_par_foo()
662 struct fb_var_screeninfo *var = &info->var; in cirrusfb_set_par_foo()
663 u8 __iomem *regbase = cinfo->regbase; in cirrusfb_set_par_foo()
673 dev_dbg(info->device, "Requested mode: %dx%dx%d\n", in cirrusfb_set_par_foo()
674 var->xres, var->yres, var->bits_per_pixel); in cirrusfb_set_par_foo()
676 switch (var->bits_per_pixel) { in cirrusfb_set_par_foo()
678 info->fix.line_length = var->xres_virtual / 8; in cirrusfb_set_par_foo()
679 info->fix.visual = FB_VISUAL_MONO10; in cirrusfb_set_par_foo()
683 info->fix.line_length = var->xres_virtual; in cirrusfb_set_par_foo()
684 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in cirrusfb_set_par_foo()
689 info->fix.line_length = var->xres_virtual * in cirrusfb_set_par_foo()
690 var->bits_per_pixel >> 3; in cirrusfb_set_par_foo()
691 info->fix.visual = FB_VISUAL_TRUECOLOR; in cirrusfb_set_par_foo()
694 info->fix.type = FB_TYPE_PACKED_PIXELS; in cirrusfb_set_par_foo()
698 bi = &cirrusfb_board_info[cinfo->btype]; in cirrusfb_set_par_foo()
700 hsyncstart = var->xres + var->right_margin; in cirrusfb_set_par_foo()
701 hsyncend = hsyncstart + var->hsync_len; in cirrusfb_set_par_foo()
702 htotal = (hsyncend + var->left_margin) / 8; in cirrusfb_set_par_foo()
703 hdispend = var->xres / 8; in cirrusfb_set_par_foo()
707 vdispend = var->yres; in cirrusfb_set_par_foo()
708 vsyncstart = vdispend + var->lower_margin; in cirrusfb_set_par_foo()
709 vsyncend = vsyncstart + var->vsync_len; in cirrusfb_set_par_foo()
710 vtotal = vsyncend + var->upper_margin; in cirrusfb_set_par_foo()
712 if (var->vmode & FB_VMODE_DOUBLE) { in cirrusfb_set_par_foo()
717 } else if (var->vmode & FB_VMODE_INTERLACED) { in cirrusfb_set_par_foo()
731 vdispend -= 1; in cirrusfb_set_par_foo()
732 vsyncstart -= 1; in cirrusfb_set_par_foo()
733 vsyncend -= 1; in cirrusfb_set_par_foo()
734 vtotal -= 2; in cirrusfb_set_par_foo()
736 if (cinfo->multiplexing) { in cirrusfb_set_par_foo()
743 htotal -= 5; in cirrusfb_set_par_foo()
744 hdispend -= 1; in cirrusfb_set_par_foo()
752 dev_dbg(info->device, "CRT0: %d\n", htotal); in cirrusfb_set_par_foo()
755 dev_dbg(info->device, "CRT1: %d\n", hdispend); in cirrusfb_set_par_foo()
758 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8); in cirrusfb_set_par_foo()
759 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8); in cirrusfb_set_par_foo()
762 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32); in cirrusfb_set_par_foo()
766 dev_dbg(info->device, "CRT4: %d\n", hsyncstart); in cirrusfb_set_par_foo()
772 dev_dbg(info->device, "CRT5: %d\n", tmp); in cirrusfb_set_par_foo()
775 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
793 dev_dbg(info->device, "CRT7: %d\n", tmp); in cirrusfb_set_par_foo()
799 if (var->vmode & FB_VMODE_DOUBLE) in cirrusfb_set_par_foo()
801 dev_dbg(info->device, "CRT9: %d\n", tmp); in cirrusfb_set_par_foo()
804 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff); in cirrusfb_set_par_foo()
807 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16); in cirrusfb_set_par_foo()
810 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff); in cirrusfb_set_par_foo()
813 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff); in cirrusfb_set_par_foo()
816 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
819 dev_dbg(info->device, "CRT18: 0xff\n"); in cirrusfb_set_par_foo()
823 if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_set_par_foo()
834 dev_dbg(info->device, "CRT1a: %d\n", tmp); in cirrusfb_set_par_foo()
837 freq = PICOS2KHZ(var->pixclock); in cirrusfb_set_par_foo()
838 if (var->bits_per_pixel == 24) in cirrusfb_set_par_foo()
839 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) in cirrusfb_set_par_foo()
841 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
843 if (cinfo->doubleVCLK) in cirrusfb_set_par_foo()
848 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n", in cirrusfb_set_par_foo()
856 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 || in cirrusfb_set_par_foo()
857 cinfo->btype == BT_SD64) { in cirrusfb_set_par_foo()
867 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
868 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
871 if (cinfo->btype == BT_LAGUNAB) { in cirrusfb_set_par_foo()
872 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
874 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
877 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
878 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
879 control = fb_readw(cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
880 threshold = fb_readw(cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
890 if ((cinfo->btype == BT_SD64) || in cirrusfb_set_par_foo()
891 (cinfo->btype == BT_ALPINE) || in cirrusfb_set_par_foo()
892 (cinfo->btype == BT_GD5480)) in cirrusfb_set_par_foo()
914 /* mode is used, but I feel better this way.. :-) */ in cirrusfb_set_par_foo()
915 if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_set_par_foo()
923 if (var->sync & FB_SYNC_HOR_HIGH_ACT) in cirrusfb_set_par_foo()
925 if (var->sync & FB_SYNC_VERT_HIGH_ACT) in cirrusfb_set_par_foo()
941 if (var->bits_per_pixel == 1) { in cirrusfb_set_par_foo()
942 dev_dbg(info->device, "preparing for 1 bit deep display\n"); in cirrusfb_set_par_foo()
946 switch (cinfo->btype) { in cirrusfb_set_par_foo()
955 cinfo->multiplexing ? in cirrusfb_set_par_foo()
956 bi->sr07_1bpp_mux : bi->sr07_1bpp); in cirrusfb_set_par_foo()
966 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
971 switch (cinfo->btype) { in cirrusfb_set_par_foo()
994 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
998 /* pixel mask: pass-through for first plane */ in cirrusfb_set_par_foo()
1000 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1018 else if (var->bits_per_pixel == 8) { in cirrusfb_set_par_foo()
1019 dev_dbg(info->device, "preparing for 8 bit deep display\n"); in cirrusfb_set_par_foo()
1020 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1029 cinfo->multiplexing ? in cirrusfb_set_par_foo()
1030 bi->sr07_8bpp_mux : bi->sr07_8bpp); in cirrusfb_set_par_foo()
1041 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1045 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1049 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1067 dev_warn(info->device, "unknown board\n"); in cirrusfb_set_par_foo()
1073 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1087 else if (var->bits_per_pixel == 16) { in cirrusfb_set_par_foo()
1088 dev_dbg(info->device, "preparing for 16 bit deep display\n"); in cirrusfb_set_par_foo()
1089 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1093 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1099 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1108 cinfo->doubleVCLK ? 0xa3 : 0xa7); in cirrusfb_set_par_foo()
1126 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1133 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); in cirrusfb_set_par_foo()
1146 else if (var->bits_per_pixel == 24) { in cirrusfb_set_par_foo()
1147 dev_dbg(info->device, "preparing for 24 bit deep display\n"); in cirrusfb_set_par_foo()
1148 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1152 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1158 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1184 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1190 /* hidden dac reg: 8-8-8 mode (24 or 32) */ in cirrusfb_set_par_foo()
1201 dev_err(info->device, in cirrusfb_set_par_foo()
1203 var->bits_per_pixel); in cirrusfb_set_par_foo()
1205 pitch = info->fix.line_length >> 3; in cirrusfb_set_par_foo()
1211 /* screen start addr #16-18, fastpagemode cycles */ in cirrusfb_set_par_foo()
1215 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) in cirrusfb_set_par_foo()
1234 dev_dbg(info->device, "CRT1e: %d\n", tmp); in cirrusfb_set_par_foo()
1246 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
1247 fb_writew(format, cinfo->laguna_mmio + 0xc0); in cirrusfb_set_par_foo()
1248 fb_writew(threshold, cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
1250 /* finally, turn on everything - turn off "FullBandwidth" bit */ in cirrusfb_set_par_foo()
1255 if (var->vmode & FB_VMODE_CLOCK_HALVE) in cirrusfb_set_par_foo()
1260 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp); in cirrusfb_set_par_foo()
1270 * the registers twice for the settings to take..grr. -dte */
1281 struct cirrusfb_info *cinfo = info->par; in cirrusfb_setcolreg()
1284 return -EINVAL; in cirrusfb_setcolreg()
1286 if (info->fix.visual == FB_VISUAL_TRUECOLOR) { in cirrusfb_setcolreg()
1288 red >>= (16 - info->var.red.length); in cirrusfb_setcolreg()
1289 green >>= (16 - info->var.green.length); in cirrusfb_setcolreg()
1290 blue >>= (16 - info->var.blue.length); in cirrusfb_setcolreg()
1294 v = (red << info->var.red.offset) | in cirrusfb_setcolreg()
1295 (green << info->var.green.offset) | in cirrusfb_setcolreg()
1296 (blue << info->var.blue.offset); in cirrusfb_setcolreg()
1298 cinfo->pseudo_palette[regno] = v; in cirrusfb_setcolreg()
1302 if (info->var.bits_per_pixel == 8) in cirrusfb_setcolreg()
1312 performs display panning - provided hardware permits this
1320 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pan_display()
1324 if (var->vmode & FB_VMODE_YWRAP) in cirrusfb_pan_display()
1325 return -EINVAL; in cirrusfb_pan_display()
1327 xoffset = var->xoffset * info->var.bits_per_pixel / 8; in cirrusfb_pan_display()
1329 base = var->yoffset * info->fix.line_length + xoffset; in cirrusfb_pan_display()
1331 if (info->var.bits_per_pixel == 1) { in cirrusfb_pan_display()
1333 xpix = (unsigned char) (var->xoffset % 8); in cirrusfb_pan_display()
1340 cirrusfb_WaitBLT(cinfo->regbase); in cirrusfb_pan_display()
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); in cirrusfb_pan_display()
1344 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); in cirrusfb_pan_display()
1347 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; in cirrusfb_pan_display()
1356 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); in cirrusfb_pan_display()
1359 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { in cirrusfb_pan_display()
1360 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); in cirrusfb_pan_display()
1365 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); in cirrusfb_pan_display()
1372 if (info->var.bits_per_pixel == 1) in cirrusfb_pan_display()
1373 vga_wattr(cinfo->regbase, CL_AR33, xpix); in cirrusfb_pan_display()
1383 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking in cirrusfb_blank()
1392 struct cirrusfb_info *cinfo = info->par; in cirrusfb_blank()
1393 int current_mode = cinfo->blank_mode; in cirrusfb_blank()
1395 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode); in cirrusfb_blank()
1397 if (info->state != FBINFO_STATE_RUNNING || in cirrusfb_blank()
1399 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1412 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; in cirrusfb_blank()
1413 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); in cirrusfb_blank()
1430 dev_dbg(info->device, "EXIT, returning 1\n"); in cirrusfb_blank()
1434 vga_wgfx(cinfo->regbase, CL_GRE, val); in cirrusfb_blank()
1436 cinfo->blank_mode = blank_mode; in cirrusfb_blank()
1437 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1449 struct cirrusfb_info *cinfo = info->par; in init_vgachip()
1454 bi = &cirrusfb_board_info[cinfo->btype]; in init_vgachip()
1457 switch (cinfo->btype) { in init_vgachip()
1477 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); in init_vgachip()
1480 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1484 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); in init_vgachip()
1488 vga_wgfx(cinfo->regbase, CL_GR33, 0x00); in init_vgachip()
1497 dev_err(info->device, "Warning: Unknown board type\n"); in init_vgachip()
1502 assert(info->screen_size > 0); in init_vgachip()
1508 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1513 if (cinfo->btype != BT_SD64) in init_vgachip()
1517 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); in init_vgachip()
1520 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); in init_vgachip()
1522 /* "magic cookie" - doesn't make any sense to me.. */ in init_vgachip()
1523 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */ in init_vgachip()
1525 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); in init_vgachip()
1527 switch (cinfo->btype) { in init_vgachip()
1529 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); in init_vgachip()
1537 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); in init_vgachip()
1541 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); in init_vgachip()
1542 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); in init_vgachip()
1547 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); in init_vgachip()
1549 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); in init_vgachip()
1551 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); in init_vgachip()
1553 /* controller-internal base address of video memory */ in init_vgachip()
1554 if (bi->init_sr07) in init_vgachip()
1555 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); in init_vgachip()
1557 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */ in init_vgachip()
1561 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); in init_vgachip()
1563 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); in init_vgachip()
1565 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); in init_vgachip()
1567 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); in init_vgachip()
1570 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1572 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); in init_vgachip()
1574 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); in init_vgachip()
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); in init_vgachip()
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); in init_vgachip()
1581 /* Text cursor end: - */ in init_vgachip()
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); in init_vgachip()
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); in init_vgachip()
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); in init_vgachip()
1588 /* Underline Row scanline: - */ in init_vgachip()
1589 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); in init_vgachip()
1592 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); in init_vgachip()
1594 /* Set/Reset registers: - */ in init_vgachip()
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); in init_vgachip()
1596 /* Set/Reset enable: - */ in init_vgachip()
1597 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); in init_vgachip()
1598 /* Color Compare: - */ in init_vgachip()
1599 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); in init_vgachip()
1600 /* Data Rotate: - */ in init_vgachip()
1601 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); in init_vgachip()
1602 /* Read Map Select: - */ in init_vgachip()
1603 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); in init_vgachip()
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); in init_vgachip()
1607 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); in init_vgachip()
1609 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); in init_vgachip()
1611 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); in init_vgachip()
1613 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 || in init_vgachip()
1616 vga_wgfx(cinfo->regbase, CL_GRB, 0x20); in init_vgachip()
1621 vga_wgfx(cinfo->regbase, CL_GRB, 0x28); in init_vgachip()
1623 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ in init_vgachip()
1624 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ in init_vgachip()
1625 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ in init_vgachip()
1626 /* Background color byte 1: - */ in init_vgachip()
1627 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */ in init_vgachip()
1628 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ in init_vgachip()
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); in init_vgachip()
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); in init_vgachip()
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); in init_vgachip()
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); in init_vgachip()
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); in init_vgachip()
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); in init_vgachip()
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); in init_vgachip()
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); in init_vgachip()
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); in init_vgachip()
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); in init_vgachip()
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); in init_vgachip()
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); in init_vgachip()
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); in init_vgachip()
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); in init_vgachip()
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); in init_vgachip()
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); in init_vgachip()
1649 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); in init_vgachip()
1651 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); in init_vgachip()
1653 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); in init_vgachip()
1654 /* Color Select: - */ in init_vgachip()
1655 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); in init_vgachip()
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x04); in init_vgachip()
1661 /* - " - : "end-of-reset" */ in init_vgachip()
1662 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1665 WHDR(cinfo, 0); /* Hidden DAC register: - */ in init_vgachip()
1674 if (cinfo->btype == BT_PICASSO4) in switch_monitor()
1676 if (cinfo->btype == BT_ALPINE) in switch_monitor()
1678 if (cinfo->btype == BT_GD5480) in switch_monitor()
1680 if (cinfo->btype == BT_PICASSO) { in switch_monitor()
1686 switch (cinfo->btype) { in switch_monitor()
1688 WSFR(cinfo, cinfo->SFR | 0x21); in switch_monitor()
1691 WSFR(cinfo, cinfo->SFR | 0x28); in switch_monitor()
1699 switch (cinfo->btype) { in switch_monitor()
1701 WSFR(cinfo, cinfo->SFR & 0xde); in switch_monitor()
1704 WSFR(cinfo, cinfo->SFR & 0xd7); in switch_monitor()
1717 /* Linux 2.6-style accelerated functions */
1722 struct cirrusfb_info *cinfo = info->par; in cirrusfb_sync()
1725 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) in cirrusfb_sync()
1736 struct cirrusfb_info *cinfo = info->par; in cirrusfb_fillrect()
1737 int m = info->var.bits_per_pixel; in cirrusfb_fillrect()
1738 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? in cirrusfb_fillrect()
1739 cinfo->pseudo_palette[region->color] : region->color; in cirrusfb_fillrect()
1741 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_fillrect()
1743 if (info->flags & FBINFO_HWACCEL_DISABLED) { in cirrusfb_fillrect()
1748 vxres = info->var.xres_virtual; in cirrusfb_fillrect()
1749 vyres = info->var.yres_virtual; in cirrusfb_fillrect()
1758 modded.width = vxres - modded.dx; in cirrusfb_fillrect()
1760 modded.height = vyres - modded.dy; in cirrusfb_fillrect()
1762 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_fillrect()
1763 info->var.bits_per_pixel, in cirrusfb_fillrect()
1764 (region->dx * m) / 8, region->dy, in cirrusfb_fillrect()
1765 (region->width * m) / 8, region->height, in cirrusfb_fillrect()
1767 info->fix.line_length, 0x40); in cirrusfb_fillrect()
1775 struct cirrusfb_info *cinfo = info->par; in cirrusfb_copyarea()
1776 int m = info->var.bits_per_pixel; in cirrusfb_copyarea()
1778 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_copyarea()
1780 if (info->flags & FBINFO_HWACCEL_DISABLED) { in cirrusfb_copyarea()
1785 vxres = info->var.xres_virtual; in cirrusfb_copyarea()
1786 vyres = info->var.yres_virtual; in cirrusfb_copyarea()
1795 modded.width = vxres - modded.sx; in cirrusfb_copyarea()
1797 modded.width = vxres - modded.dx; in cirrusfb_copyarea()
1799 modded.height = vyres - modded.sy; in cirrusfb_copyarea()
1801 modded.height = vyres - modded.dy; in cirrusfb_copyarea()
1803 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, in cirrusfb_copyarea()
1804 (area->sx * m) / 8, area->sy, in cirrusfb_copyarea()
1805 (area->dx * m) / 8, area->dy, in cirrusfb_copyarea()
1806 (area->width * m) / 8, area->height, in cirrusfb_copyarea()
1807 info->fix.line_length); in cirrusfb_copyarea()
1814 struct cirrusfb_info *cinfo = info->par; in cirrusfb_imageblit()
1815 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4; in cirrusfb_imageblit()
1817 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_imageblit()
1819 /* Alpine/SD64 does not work at 24bpp ??? */ in cirrusfb_imageblit()
1820 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) in cirrusfb_imageblit()
1822 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) && in cirrusfb_imageblit()
1826 unsigned size = ((image->width + 7) >> 3) * image->height; in cirrusfb_imageblit()
1827 int m = info->var.bits_per_pixel; in cirrusfb_imageblit()
1830 if (info->var.bits_per_pixel == 8) { in cirrusfb_imageblit()
1831 fg = image->fg_color; in cirrusfb_imageblit()
1832 bg = image->bg_color; in cirrusfb_imageblit()
1834 fg = ((u32 *)(info->pseudo_palette))[image->fg_color]; in cirrusfb_imageblit()
1835 bg = ((u32 *)(info->pseudo_palette))[image->bg_color]; in cirrusfb_imageblit()
1837 if (info->var.bits_per_pixel == 24) { in cirrusfb_imageblit()
1839 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1840 info->var.bits_per_pixel, in cirrusfb_imageblit()
1841 (image->dx * m) / 8, image->dy, in cirrusfb_imageblit()
1842 (image->width * m) / 8, in cirrusfb_imageblit()
1843 image->height, in cirrusfb_imageblit()
1845 info->fix.line_length, 0x40); in cirrusfb_imageblit()
1847 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1848 info->var.bits_per_pixel, in cirrusfb_imageblit()
1849 (image->dx * m) / 8, image->dy, in cirrusfb_imageblit()
1850 (image->width * m) / 8, image->height, in cirrusfb_imageblit()
1852 info->fix.line_length, op); in cirrusfb_imageblit()
1853 memcpy(info->screen_base, image->data, size); in cirrusfb_imageblit()
1868 struct cirrusfb_info *cinfo = info->par; in cirrusfb_get_memsize()
1883 /* 64-bit DRAM data bus width; assume 2MB. in cirrusfb_get_memsize()
1890 dev_warn(info->device, "Unknown memory size!\n"); in cirrusfb_get_memsize()
1896 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) in cirrusfb_get_memsize()
1914 /* This is a best-guess for now */ in get_pci_addrs()
1929 struct pci_dev *pdev = to_pci_dev(info->device); in cirrusfb_pci_unmap()
1930 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pci_unmap()
1932 if (cinfo->laguna_mmio == NULL) in cirrusfb_pci_unmap()
1933 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_unmap()
1934 iounmap(info->screen_base); in cirrusfb_pci_unmap()
1935 #if 0 /* if system didn't claim this region, we would... */ in cirrusfb_pci_unmap()
1947 struct cirrusfb_info *cinfo = info->par; in cirrusfb_zorro_unmap()
1948 struct zorro_dev *zdev = to_zorro_dev(info->device); in cirrusfb_zorro_unmap()
1950 if (info->fix.smem_start > 16 * MB_) in cirrusfb_zorro_unmap()
1951 iounmap(info->screen_base); in cirrusfb_zorro_unmap()
1952 if (info->fix.mmio_start > 16 * MB_) in cirrusfb_zorro_unmap()
1953 iounmap(cinfo->regbase); in cirrusfb_zorro_unmap()
1977 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_fbinfo()
1978 struct fb_var_screeninfo *var = &info->var; in cirrusfb_set_fbinfo()
1980 info->pseudo_palette = cinfo->pseudo_palette; in cirrusfb_set_fbinfo()
1981 info->flags = FBINFO_HWACCEL_XPAN in cirrusfb_set_fbinfo()
1987 info->flags |= FBINFO_HWACCEL_DISABLED; in cirrusfb_set_fbinfo()
1988 info->fix.accel = FB_ACCEL_NONE; in cirrusfb_set_fbinfo()
1990 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE; in cirrusfb_set_fbinfo()
1992 info->fbops = &cirrusfb_ops; in cirrusfb_set_fbinfo()
1994 if (cinfo->btype == BT_GD5480) { in cirrusfb_set_fbinfo()
1995 if (var->bits_per_pixel == 16) in cirrusfb_set_fbinfo()
1996 info->screen_base += 1 * MB_; in cirrusfb_set_fbinfo()
1997 if (var->bits_per_pixel == 32) in cirrusfb_set_fbinfo()
1998 info->screen_base += 2 * MB_; in cirrusfb_set_fbinfo()
2002 strscpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name, in cirrusfb_set_fbinfo()
2003 sizeof(info->fix.id)); in cirrusfb_set_fbinfo()
2007 info->fix.smem_len = info->screen_size; in cirrusfb_set_fbinfo()
2008 if (var->bits_per_pixel == 1) in cirrusfb_set_fbinfo()
2009 info->fix.smem_len /= 4; in cirrusfb_set_fbinfo()
2010 info->fix.type_aux = 0; in cirrusfb_set_fbinfo()
2011 info->fix.xpanstep = 1; in cirrusfb_set_fbinfo()
2012 info->fix.ypanstep = 1; in cirrusfb_set_fbinfo()
2013 info->fix.ywrapstep = 0; in cirrusfb_set_fbinfo()
2016 info->fix.mmio_len = 0; in cirrusfb_set_fbinfo()
2018 fb_alloc_cmap(&info->cmap, 256, 0); in cirrusfb_set_fbinfo()
2025 struct cirrusfb_info *cinfo = info->par; in cirrusfb_register()
2029 assert(cinfo->btype != BT_NONE); in cirrusfb_register()
2034 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base); in cirrusfb_register()
2036 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); in cirrusfb_register()
2038 dev_dbg(info->device, "wrong initial video mode\n"); in cirrusfb_register()
2039 err = -EINVAL; in cirrusfb_register()
2043 info->var.activate = FB_ACTIVATE_NOW; in cirrusfb_register()
2045 err = cirrusfb_check_var(&info->var, info); in cirrusfb_register()
2048 dev_dbg(info->device, in cirrusfb_register()
2055 dev_err(info->device, in cirrusfb_register()
2063 fb_dealloc_cmap(&info->cmap); in cirrusfb_register()
2069 struct cirrusfb_info *cinfo = info->par; in cirrusfb_cleanup()
2073 fb_dealloc_cmap(&info->cmap); in cirrusfb_cleanup()
2074 dev_dbg(info->device, "Framebuffer unregistered\n"); in cirrusfb_cleanup()
2075 cinfo->unmap(info); in cirrusfb_cleanup()
2098 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev); in cirrusfb_pci_register()
2100 ret = -ENOMEM; in cirrusfb_pci_register()
2104 cinfo = info->par; in cirrusfb_pci_register()
2105 cinfo->btype = (enum cirrus_board) ent->driver_data; in cirrusfb_pci_register()
2107 dev_dbg(info->device, in cirrusfb_pci_register()
2109 (unsigned long long)pdev->resource[0].start, cinfo->btype); in cirrusfb_pci_register()
2110 dev_dbg(info->device, " base address 1 is 0x%Lx\n", in cirrusfb_pci_register()
2111 (unsigned long long)pdev->resource[1].start); in cirrusfb_pci_register()
2113 dev_dbg(info->device, in cirrusfb_pci_register()
2115 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start); in cirrusfb_pci_register()
2117 cinfo->regbase = NULL; in cirrusfb_pci_register()
2118 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); in cirrusfb_pci_register()
2120 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n", in cirrusfb_pci_register()
2121 board_addr, info->fix.mmio_start); in cirrusfb_pci_register()
2123 board_size = (cinfo->btype == BT_GD5480) ? in cirrusfb_pci_register()
2124 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); in cirrusfb_pci_register()
2128 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2132 #if 0 /* if the system didn't claim this region, we would... */ in cirrusfb_pci_register()
2134 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2136 ret = -EBUSY; in cirrusfb_pci_register()
2143 info->screen_base = ioremap(board_addr, board_size); in cirrusfb_pci_register()
2144 if (!info->screen_base) { in cirrusfb_pci_register()
2145 ret = -EIO; in cirrusfb_pci_register()
2149 info->fix.smem_start = board_addr; in cirrusfb_pci_register()
2150 info->screen_size = board_size; in cirrusfb_pci_register()
2151 cinfo->unmap = cirrusfb_pci_unmap; in cirrusfb_pci_register()
2153 dev_info(info->device, in cirrusfb_pci_register()
2155 info->screen_size >> 10, board_addr); in cirrusfb_pci_register()
2162 iounmap(info->screen_base); in cirrusfb_pci_register()
2172 if (cinfo->laguna_mmio != NULL) in cirrusfb_pci_register()
2173 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_register()
2205 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev); in cirrusfb_zorro_register()
2207 return -ENOMEM; in cirrusfb_zorro_register()
2209 zcl = (const struct zorrocl *)ent->driver_data; in cirrusfb_zorro_register()
2210 btype = zcl->type; in cirrusfb_zorro_register()
2211 regbase = zorro_resource_start(z) + zcl->regoffset; in cirrusfb_zorro_register()
2212 ramsize = zcl->ramsize; in cirrusfb_zorro_register()
2214 rambase = zorro_resource_start(z) + zcl->ramoffset; in cirrusfb_zorro_register()
2217 rambase += zcl->ramoffset; in cirrusfb_zorro_register()
2220 struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL); in cirrusfb_zorro_register()
2222 dev_err(info->device, "No video RAM found\n"); in cirrusfb_zorro_register()
2223 error = -ENODEV; in cirrusfb_zorro_register()
2228 if (zcl->ramid2 && in cirrusfb_zorro_register()
2229 (ram = zorro_find_device(zcl->ramid2, NULL))) { in cirrusfb_zorro_register()
2231 dev_warn(info->device, in cirrusfb_zorro_register()
2232 "Skipping non-contiguous RAM at %pR\n", in cirrusfb_zorro_register()
2233 &ram->resource); in cirrusfb_zorro_register()
2240 dev_info(info->device, in cirrusfb_zorro_register()
2246 dev_err(info->device, "Cannot reserve %pR\n", &z->resource); in cirrusfb_zorro_register()
2247 error = -EBUSY; in cirrusfb_zorro_register()
2251 cinfo = info->par; in cirrusfb_zorro_register()
2252 cinfo->btype = btype; in cirrusfb_zorro_register()
2254 info->fix.mmio_start = regbase; in cirrusfb_zorro_register()
2255 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) in cirrusfb_zorro_register()
2257 if (!cinfo->regbase) { in cirrusfb_zorro_register()
2258 dev_err(info->device, "Cannot map registers\n"); in cirrusfb_zorro_register()
2259 error = -EIO; in cirrusfb_zorro_register()
2263 info->fix.smem_start = rambase; in cirrusfb_zorro_register()
2264 info->screen_size = ramsize; in cirrusfb_zorro_register()
2265 info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize) in cirrusfb_zorro_register()
2267 if (!info->screen_base) { in cirrusfb_zorro_register()
2268 dev_err(info->device, "Cannot map video RAM\n"); in cirrusfb_zorro_register()
2269 error = -EIO; in cirrusfb_zorro_register()
2273 cinfo->unmap = cirrusfb_zorro_unmap; in cirrusfb_zorro_register()
2275 dev_info(info->device, in cirrusfb_zorro_register()
2281 vga_wseq(cinfo->regbase, CL_SEQR1F, in cirrusfb_zorro_register()
2286 dev_err(info->device, "Failed to register device, error %d\n", in cirrusfb_zorro_register()
2296 iounmap(info->screen_base); in cirrusfb_zorro_register()
2300 iounmap(cinfo->regbase); in cirrusfb_zorro_register()
2364 return -ENODEV; in cirrusfb_init()
2368 return -ENODEV; in cirrusfb_init()
2394 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2403 /* about the following functions - I have used the same names for the */
2409 /*** WGen() - write into one of the external/general registers ***/
2415 if (cinfo->btype == BT_PICASSO) { in WGen()
2423 vga_w(cinfo->regbase, regofs + regnum, val); in WGen()
2426 /*** RGen() - read out one of the external/general registers ***/
2431 if (cinfo->btype == BT_PICASSO) { in RGen()
2439 return vga_r(cinfo->regbase, regofs + regnum); in RGen()
2442 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2447 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { in AttrOn()
2450 vga_w(cinfo->regbase, VGA_ATT_IW, in AttrOn()
2451 vga_r(cinfo->regbase, VGA_ATT_R)); in AttrOn()
2454 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */ in AttrOn()
2455 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); in AttrOn()
2458 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); in AttrOn()
2461 /*** WHDR() - write into the Hidden DAC register ***/
2464 * registers of their functional group) here is a specialized routine for
2471 if (cinfo->btype == BT_PICASSO) { in WHDR()
2494 if (cinfo->btype == BT_PICASSO) { in WHDR()
2506 /*** WSFR() - write to the "special function register" (SFR) ***/
2510 assert(cinfo->regbase != NULL); in WSFR()
2511 cinfo->SFR = val; in WSFR()
2512 z_writeb(val, cinfo->regbase + 0x8000); in WSFR()
2522 assert(cinfo->regbase != NULL); in WSFR2()
2523 cinfo->SFR = val; in WSFR2()
2524 z_writeb(val, cinfo->regbase + 0x9000); in WSFR2()
2528 /*** WClut - set CLUT entry (range: 0..63) ***/
2535 vga_w(cinfo->regbase, VGA_PEL_IW, regnum); in WClut()
2537 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || in WClut()
2538 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 || in WClut()
2539 cinfo->btype == BT_SD64 || is_laguna(cinfo)) { in WClut()
2541 if (cinfo->btype == BT_PICASSO) in WClut()
2543 vga_w(cinfo->regbase, data, red); in WClut()
2544 vga_w(cinfo->regbase, data, green); in WClut()
2545 vga_w(cinfo->regbase, data, blue); in WClut()
2547 vga_w(cinfo->regbase, data, blue); in WClut()
2548 vga_w(cinfo->regbase, data, green); in WClut()
2549 vga_w(cinfo->regbase, data, red); in WClut()
2554 /*** RClut - read CLUT entry (range 0..63) ***/
2560 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2562 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2563 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2564 if (cinfo->btype == BT_PICASSO)
2566 *red = vga_r(cinfo->regbase, data);
2567 *green = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2570 *blue = vga_r(cinfo->regbase, data);
2571 *green = vga_r(cinfo->regbase, data);
2572 *red = vga_r(cinfo->regbase, data);
2612 /* BLT width: actual number of pixels - 1 */ in cirrusfb_set_blitter()
2618 /* BLT height: actual number of lines -1 */ in cirrusfb_set_blitter()
2662 u_short nwidth = width - 1; in cirrusfb_BitBLT()
2663 u_short nheight = height - 1; in cirrusfb_BitBLT()
2731 cirrusfb_set_blitter(regbase, width - 1, height - 1, in cirrusfb_RectFill()
2736 * bestclock() - determine closest possible clock lower(?) than the
2769 h = h > freq ? h - freq : freq - h; in bestclock()
2784 h = h > freq ? h - freq : freq - h; in bestclock()
2795 /* -------------------------------------------------------------------------
2799 * -------------------------------------------------------------------------
2811 * old-style I/O ports are queried for information, otherwise MMIO is
2843 dev_dbg(info->device, "%8s = 0x%02X\n", name, val); in cirrusfb_dbg_print_regs()
2857 * old-style I/O ports are queried for information, otherwise MMIO is
2863 dev_dbg(info->device, "VGA CRTC register dump:\n"); in cirrusfb_dbg_reg_dump()
2915 dev_dbg(info->device, "\n"); in cirrusfb_dbg_reg_dump()
2917 dev_dbg(info->device, "VGA SEQ register dump:\n"); in cirrusfb_dbg_reg_dump()
2948 dev_dbg(info->device, "\n"); in cirrusfb_dbg_reg_dump()