Lines Matching refs:save_regs
563 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); in radeon_pm_save_regs()
564 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); in radeon_pm_save_regs()
565 rinfo->save_regs[2] = INPLL(MCLK_CNTL); in radeon_pm_save_regs()
566 rinfo->save_regs[3] = INPLL(SCLK_CNTL); in radeon_pm_save_regs()
567 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); in radeon_pm_save_regs()
568 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); in radeon_pm_save_regs()
569 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); in radeon_pm_save_regs()
570 rinfo->save_regs[7] = INPLL(MCLK_MISC); in radeon_pm_save_regs()
571 rinfo->save_regs[8] = INPLL(P2PLL_CNTL); in radeon_pm_save_regs()
573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()
574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()
575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
576 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); in radeon_pm_save_regs()
577 rinfo->save_regs[14] = INREG(BUS_CNTL1); in radeon_pm_save_regs()
578 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); in radeon_pm_save_regs()
579 rinfo->save_regs[16] = INREG(AGP_CNTL); in radeon_pm_save_regs()
580 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
581 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
582 rinfo->save_regs[19] = INREG(GPIOPAD_A); in radeon_pm_save_regs()
583 rinfo->save_regs[20] = INREG(GPIOPAD_EN); in radeon_pm_save_regs()
584 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); in radeon_pm_save_regs()
585 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); in radeon_pm_save_regs()
586 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); in radeon_pm_save_regs()
587 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); in radeon_pm_save_regs()
588 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); in radeon_pm_save_regs()
589 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); in radeon_pm_save_regs()
590 rinfo->save_regs[27] = INREG(GPIO_MONID); in radeon_pm_save_regs()
591 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); in radeon_pm_save_regs()
593 rinfo->save_regs[29] = INREG(SURFACE_CNTL); in radeon_pm_save_regs()
594 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); in radeon_pm_save_regs()
595 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
596 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); in radeon_pm_save_regs()
597 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
599 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); in radeon_pm_save_regs()
600 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); in radeon_pm_save_regs()
601 rinfo->save_regs[36] = INREG(BUS_CNTL); in radeon_pm_save_regs()
602 rinfo->save_regs[39] = INREG(RBBM_CNTL); in radeon_pm_save_regs()
603 rinfo->save_regs[40] = INREG(DAC_CNTL); in radeon_pm_save_regs()
604 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); in radeon_pm_save_regs()
605 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); in radeon_pm_save_regs()
606 rinfo->save_regs[38] = INREG(FCP_CNTL); in radeon_pm_save_regs()
609 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); in radeon_pm_save_regs()
610 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); in radeon_pm_save_regs()
611 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); in radeon_pm_save_regs()
612 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); in radeon_pm_save_regs()
613 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); in radeon_pm_save_regs()
614 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); in radeon_pm_save_regs()
615 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
619 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); in radeon_pm_save_regs()
620 rinfo->save_regs[46] = INREG(MC_CNTL); in radeon_pm_save_regs()
621 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); in radeon_pm_save_regs()
622 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); in radeon_pm_save_regs()
623 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); in radeon_pm_save_regs()
624 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); in radeon_pm_save_regs()
625 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); in radeon_pm_save_regs()
626 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); in radeon_pm_save_regs()
627 rinfo->save_regs[53] = INREG(MC_DEBUG); in radeon_pm_save_regs()
629 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); in radeon_pm_save_regs()
630 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); in radeon_pm_save_regs()
631 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); in radeon_pm_save_regs()
632 rinfo->save_regs[57] = INREG(FW_CNTL); in radeon_pm_save_regs()
635 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER); in radeon_pm_save_regs()
636 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL); in radeon_pm_save_regs()
637 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0); in radeon_pm_save_regs()
638 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1); in radeon_pm_save_regs()
639 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0); in radeon_pm_save_regs()
640 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1); in radeon_pm_save_regs()
641 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3); in radeon_pm_save_regs()
642 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0); in radeon_pm_save_regs()
643 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1); in radeon_pm_save_regs()
644 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0); in radeon_pm_save_regs()
645 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1); in radeon_pm_save_regs()
646 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL); in radeon_pm_save_regs()
647 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL); in radeon_pm_save_regs()
648 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0); in radeon_pm_save_regs()
649 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL); in radeon_pm_save_regs()
650 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD); in radeon_pm_save_regs()
652 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL); in radeon_pm_save_regs()
653 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0); in radeon_pm_save_regs()
654 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1); in radeon_pm_save_regs()
655 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0); in radeon_pm_save_regs()
656 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1); in radeon_pm_save_regs()
657 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0); in radeon_pm_save_regs()
660 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); in radeon_pm_save_regs()
661 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
662 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); in radeon_pm_save_regs()
663 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); in radeon_pm_save_regs()
664 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); in radeon_pm_save_regs()
665 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); in radeon_pm_save_regs()
666 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); in radeon_pm_save_regs()
668 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); in radeon_pm_save_regs()
669 rinfo->save_regs[82] = INREG(FP_GEN_CNTL); in radeon_pm_save_regs()
670 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); in radeon_pm_save_regs()
671 rinfo->save_regs[84] = INREG(TMDS_CNTL); in radeon_pm_save_regs()
672 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); in radeon_pm_save_regs()
673 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); in radeon_pm_save_regs()
674 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); in radeon_pm_save_regs()
675 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); in radeon_pm_save_regs()
676 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); in radeon_pm_save_regs()
677 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); in radeon_pm_save_regs()
678 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); in radeon_pm_save_regs()
679 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); in radeon_pm_save_regs()
680 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); in radeon_pm_save_regs()
681 rinfo->save_regs[96] = INREG(HDP_DEBUG); in radeon_pm_save_regs()
682 rinfo->save_regs[97] = INPLL(pllMDLL_CKO); in radeon_pm_save_regs()
683 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); in radeon_pm_save_regs()
684 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); in radeon_pm_save_regs()
689 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */ in radeon_pm_restore_regs()
691 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_pm_restore_regs()
692 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); in radeon_pm_restore_regs()
693 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]); in radeon_pm_restore_regs()
694 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]); in radeon_pm_restore_regs()
695 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_pm_restore_regs()
696 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]); in radeon_pm_restore_regs()
697 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]); in radeon_pm_restore_regs()
698 OUTPLL(MCLK_MISC, rinfo->save_regs[7]); in radeon_pm_restore_regs()
700 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_restore_regs()
702 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_pm_restore_regs()
703 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_pm_restore_regs()
704 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_pm_restore_regs()
705 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_pm_restore_regs()
706 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_pm_restore_regs()
709 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_pm_restore_regs()
710 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); in radeon_pm_restore_regs()
711 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); in radeon_pm_restore_regs()
712 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); in radeon_pm_restore_regs()
713 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); in radeon_pm_restore_regs()
714 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_pm_restore_regs()
715 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); in radeon_pm_restore_regs()
716 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_pm_restore_regs()
717 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); in radeon_pm_restore_regs()
718 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); in radeon_pm_restore_regs()
719 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]); in radeon_pm_restore_regs()
721 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_pm_restore_regs()
722 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_pm_restore_regs()
723 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_pm_restore_regs()
724 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); in radeon_pm_restore_regs()
725 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); in radeon_pm_restore_regs()
726 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); in radeon_pm_restore_regs()
727 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); in radeon_pm_restore_regs()
728 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); in radeon_pm_restore_regs()
729 OUTREG(GPIO_MONID, rinfo->save_regs[27]); in radeon_pm_restore_regs()
730 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); in radeon_pm_restore_regs()
1203 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_pm_enable_dll_m10()
1269 u32 sdram_mode_reg = rinfo->save_regs[35]; in radeon_pm_full_reset_sdram()
1490 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); in radeon_pm_start_mclk_sclk()
1510 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; in radeon_pm_start_mclk_sclk()
1525 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); in radeon_pm_start_mclk_sclk()
1544 tmp |= rinfo->save_regs[2] & 0xffff; in radeon_pm_start_mclk_sclk()
1569 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3); in radeon_pm_m10_disable_spread_spectrum()
1593 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3); in radeon_pm_m10_enable_lvds_spread_spectrum()
1596 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1597 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1605 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1621 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1622 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]); in radeon_pm_m10_enable_lvds_spread_spectrum()
1665 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_pm_restore_pixel_pll()
1691 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m10_reconfigure_mc()
1692 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m10_reconfigure_mc()
1693 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m10_reconfigure_mc()
1695 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_m10_reconfigure_mc()
1696 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m10_reconfigure_mc()
1697 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m10_reconfigure_mc()
1698 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m10_reconfigure_mc()
1699 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m10_reconfigure_mc()
1700 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m10_reconfigure_mc()
1701 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m10_reconfigure_mc()
1703 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]); in radeon_pm_m10_reconfigure_mc()
1704 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]); in radeon_pm_m10_reconfigure_mc()
1705 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]); in radeon_pm_m10_reconfigure_mc()
1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]); in radeon_pm_m10_reconfigure_mc()
1707 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]); in radeon_pm_m10_reconfigure_mc()
1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]); in radeon_pm_m10_reconfigure_mc()
1709 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]); in radeon_pm_m10_reconfigure_mc()
1710 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]); in radeon_pm_m10_reconfigure_mc()
1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]); in radeon_pm_m10_reconfigure_mc()
1712 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]); in radeon_pm_m10_reconfigure_mc()
1713 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]); in radeon_pm_m10_reconfigure_mc()
1714 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]); in radeon_pm_m10_reconfigure_mc()
1715 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_pm_m10_reconfigure_mc()
1716 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]); in radeon_pm_m10_reconfigure_mc()
1717 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]); in radeon_pm_m10_reconfigure_mc()
1718 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]); in radeon_pm_m10_reconfigure_mc()
1727 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M10()
1728 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M10()
1729 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M10()
1730 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M10()
1731 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M10()
1733 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M10()
1734 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M10()
1735 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M10()
1736 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M10()
1737 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M10()
1738 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M10()
1770 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M10()
1771 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); in radeon_reinitialize_M10()
1772 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M10()
1775 tmp = rinfo->save_regs[1] in radeon_reinitialize_M10()
1780 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); in radeon_reinitialize_M10()
1781 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M10()
1782 OUTREG(HDP_DEBUG, rinfo->save_regs[96]); in radeon_reinitialize_M10()
1783 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M10()
1784 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M10()
1785 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M10()
1802 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M10()
1805 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M10()
1854 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M10()
1855 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M10()
1856 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M10()
1859 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M10()
1860 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M10()
1861 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M10()
1862 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
1865 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); in radeon_reinitialize_M10()
1868 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff); in radeon_reinitialize_M10()
1874 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]); in radeon_reinitialize_M10()
1909 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); in radeon_reinitialize_M10()
1910 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); in radeon_reinitialize_M10()
1913 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M10()
1915 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M10()
1917 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); in radeon_reinitialize_M10()
1920 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M10()
1921 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M10()
1922 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M10()
1933 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M10()
1934 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M10()
1952 OUTREG(MC_CNTL, rinfo->save_regs[46]); in radeon_pm_m9p_reconfigure_mc()
1953 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); in radeon_pm_m9p_reconfigure_mc()
1954 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); in radeon_pm_m9p_reconfigure_mc()
1956 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_m9p_reconfigure_mc()
1957 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); in radeon_pm_m9p_reconfigure_mc()
1958 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); in radeon_pm_m9p_reconfigure_mc()
1959 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); in radeon_pm_m9p_reconfigure_mc()
1960 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); in radeon_pm_m9p_reconfigure_mc()
1961 OUTREG(MC_DEBUG, rinfo->save_regs[53]); in radeon_pm_m9p_reconfigure_mc()
1962 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); in radeon_pm_m9p_reconfigure_mc()
1964 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/); in radeon_pm_m9p_reconfigure_mc()
1965 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/); in radeon_pm_m9p_reconfigure_mc()
1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/); in radeon_pm_m9p_reconfigure_mc()
1967 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/); in radeon_pm_m9p_reconfigure_mc()
1968 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/); in radeon_pm_m9p_reconfigure_mc()
1969 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/); in radeon_pm_m9p_reconfigure_mc()
1981 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); in radeon_reinitialize_M9P()
1982 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); in radeon_reinitialize_M9P()
1983 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); in radeon_reinitialize_M9P()
1984 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); in radeon_reinitialize_M9P()
1985 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); in radeon_reinitialize_M9P()
1986 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); in radeon_reinitialize_M9P()
1987 OUTREG(BUS_CNTL, rinfo->save_regs[36]); in radeon_reinitialize_M9P()
1988 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); in radeon_reinitialize_M9P()
1989 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); in radeon_reinitialize_M9P()
1990 OUTREG(FCP_CNTL, rinfo->save_regs[38]); in radeon_reinitialize_M9P()
1991 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); in radeon_reinitialize_M9P()
1993 OUTREG(DAC_CNTL, rinfo->save_regs[40]); in radeon_reinitialize_M9P()
2020 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]); in radeon_reinitialize_M9P()
2022 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); in radeon_reinitialize_M9P()
2023 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); in radeon_reinitialize_M9P()
2024 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); in radeon_reinitialize_M9P()
2026 OUTREG(AGP_CNTL, rinfo->save_regs[16]); in radeon_reinitialize_M9P()
2027 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ in radeon_reinitialize_M9P()
2028 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); in radeon_reinitialize_M9P()
2030 tmp = rinfo->save_regs[1] in radeon_reinitialize_M9P()
2035 OUTREG(FW_CNTL, rinfo->save_regs[57]); in radeon_reinitialize_M9P()
2042 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); in radeon_reinitialize_M9P()
2045 tmp = rinfo->save_regs[2] & 0xff000000; in radeon_reinitialize_M9P()
2084 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); in radeon_reinitialize_M9P()
2085 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); in radeon_reinitialize_M9P()
2086 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); in radeon_reinitialize_M9P()
2089 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); in radeon_reinitialize_M9P()
2090 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); in radeon_reinitialize_M9P()
2093 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); in radeon_reinitialize_M9P()
2094 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()
2103 tmp = rinfo->save_regs[0]; in radeon_reinitialize_M9P()
2141 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); in radeon_reinitialize_M9P()
2142 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); in radeon_reinitialize_M9P()
2149 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); in radeon_reinitialize_M9P()
2150 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); in radeon_reinitialize_M9P()
2151 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); in radeon_reinitialize_M9P()
2157 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2162 tmp |= rinfo->save_regs[34] & 0xffff0000; in radeon_reinitialize_M9P()
2166 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & in radeon_reinitialize_M9P()
2169 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); in radeon_reinitialize_M9P()
2177 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */); in radeon_reinitialize_M9P()
2178 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); in radeon_reinitialize_M9P()
2190 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/ in radeon_reinitialize_M9P()
2195 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); in radeon_reinitialize_M9P()
2202 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); in radeon_reinitialize_M9P()
2203 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); in radeon_reinitialize_M9P()
2220 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2221 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2222 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2223 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2224 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2225 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2241 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2242 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2243 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2244 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2386 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2387 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2388 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2719 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) || in radeon_check_power_loss()
2720 rinfo->save_regs[2] != INPLL(MCLK_CNTL) || in radeon_check_power_loss()
2721 rinfo->save_regs[3] != INPLL(SCLK_CNTL); in radeon_check_power_loss()