Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012-2014 Freescale Semiconductor, Inc.
47 #define BM_USBPHY_CTRL_SFTRST BIT(31)
48 #define BM_USBPHY_CTRL_CLKGATE BIT(30)
49 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
50 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
51 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
52 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
53 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
54 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
55 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
56 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
57 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
58 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
59 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
60 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
62 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18))
64 #define BM_USBPHY_DEBUG_CLKGATE BIT(30)
66 #define BM_USBPHY_PLL_LOCK BIT(31)
67 #define BM_USBPHY_PLL_REG_ENABLE BIT(21)
68 #define BM_USBPHY_PLL_BYPASS BIT(16)
69 #define BM_USBPHY_PLL_POWER BIT(12)
70 #define BM_USBPHY_PLL_EN_USB_CLKS BIT(6)
72 /* Anatop Registers */
80 #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20)
81 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19)
82 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18)
85 #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
88 #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2)
89 #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1)
90 #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0)
96 #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0)
104 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
105 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
107 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
108 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
110 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
111 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
112 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
113 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
115 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
116 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
117 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
118 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
123 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
130 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
136 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
144 #define MXS_PHY_NEED_IP_FIX BIT(3)
188 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
189 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
190 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
191 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
192 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
193 { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, },
194 { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, },
211 return mxs_phy->data == &imx6q_phy_data; in is_imx6q_phy()
216 return mxs_phy->data == &imx6sl_phy_data; in is_imx6sl_phy()
221 return mxs_phy->data == &imx7ulp_phy_data; in is_imx7ulp_phy()
235 void __iomem *base = mxs_phy->phy.io_priv; in mxs_phy_tx_init()
239 if (mxs_phy->tx_reg_mask) { in mxs_phy_tx_init()
241 phytx &= ~mxs_phy->tx_reg_mask; in mxs_phy_tx_init()
242 phytx |= mxs_phy->tx_reg_set; in mxs_phy_tx_init()
247 static int mxs_phy_pll_enable(void __iomem *base, bool enable) in mxs_phy_pll_enable() argument
251 if (enable) { in mxs_phy_pll_enable()
279 void __iomem *base = mxs_phy->phy.io_priv; in mxs_phy_hw_init()
296 * - Auto clock/power on in mxs_phy_hw_init()
297 * - Enable full/low speed support in mxs_phy_hw_init()
308 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) in mxs_phy_hw_init()
311 if (mxs_phy->regmap_anatop) { in mxs_phy_hw_init()
312 unsigned int reg = mxs_phy->port_id ? in mxs_phy_hw_init()
319 regmap_write(mxs_phy->regmap_anatop, reg, in mxs_phy_hw_init()
339 if (!mxs_phy->regmap_anatop) in mxs_phy_get_vbus_status()
342 if (mxs_phy->port_id == 0) in mxs_phy_get_vbus_status()
343 regmap_read(mxs_phy->regmap_anatop, in mxs_phy_get_vbus_status()
346 else if (mxs_phy->port_id == 1) in mxs_phy_get_vbus_status()
347 regmap_read(mxs_phy->regmap_anatop, in mxs_phy_get_vbus_status()
359 void __iomem *base = mxs_phy->phy.io_priv; in __mxs_phy_disconnect_line()
366 if (mxs_phy->port_id == 0) { in __mxs_phy_disconnect_line()
369 regmap_write(mxs_phy->regmap_anatop, reg, in __mxs_phy_disconnect_line()
372 } else if (mxs_phy->port_id == 1) { in __mxs_phy_disconnect_line()
375 regmap_write(mxs_phy->regmap_anatop, reg, in __mxs_phy_disconnect_line()
391 return mxs_phy->phy.last_event == USB_EVENT_ID; in mxs_phy_is_otg_host()
397 enum usb_phy_events last_event = mxs_phy->phy.last_event; in mxs_phy_disconnect_line()
400 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) in mxs_phy_disconnect_line()
403 /* If the SoCs don't have anatop, quit */ in mxs_phy_disconnect_line()
404 if (!mxs_phy->regmap_anatop) in mxs_phy_disconnect_line()
423 ret = clk_prepare_enable(mxs_phy->clk); in mxs_phy_init()
442 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_shutdown()
443 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); in mxs_phy_shutdown()
446 phy->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_shutdown()
449 mxs_phy_pll_enable(phy->io_priv, false); in mxs_phy_shutdown()
451 clk_disable_unprepare(mxs_phy->clk); in mxs_phy_shutdown()
457 /* bit definition is the same for all controllers */ in mxs_phy_is_low_speed_connection()
462 /* If the SoCs don't have anatop, quit */ in mxs_phy_is_low_speed_connection()
463 if (!mxs_phy->regmap_anatop) in mxs_phy_is_low_speed_connection()
466 if (mxs_phy->port_id == 0) in mxs_phy_is_low_speed_connection()
468 else if (mxs_phy->port_id == 1) in mxs_phy_is_low_speed_connection()
471 regmap_read(mxs_phy->regmap_anatop, reg, &line_state); in mxs_phy_is_low_speed_connection()
490 * FIXME: Do not power down RXPWD1PT1 bit for low speed in mxs_phy_suspend()
500 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
502 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
505 x->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_suspend()
506 clk_disable_unprepare(mxs_phy->clk); in mxs_phy_suspend()
509 ret = clk_prepare_enable(mxs_phy->clk); in mxs_phy_suspend()
513 x->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_suspend()
514 writel(0, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
528 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_set_wakeup()
530 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_set_wakeup()
540 dev_dbg(phy->dev, "%s device has connected\n", in mxs_phy_on_connect()
545 phy->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_on_connect()
553 dev_dbg(phy->dev, "%s device has disconnected\n", in mxs_phy_on_disconnect()
557 if (readl(phy->io_priv + HW_USBPHY_CTRL) & in mxs_phy_on_disconnect()
560 phy->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_on_disconnect()
568 struct regmap *regmap = x->regmap_anatop; in mxs_charger_data_contact_detect()
575 dev_err(x->phy.dev, "vbus is not valid\n"); in mxs_charger_data_contact_detect()
576 return -EINVAL; in mxs_charger_data_contact_detect()
579 /* Enable charger detector */ in mxs_charger_data_contact_detect()
583 * - Do not check whether a charger is connected to the USB port in mxs_charger_data_contact_detect()
584 * - Check whether the USB plug has been in contact with each other in mxs_charger_data_contact_detect()
607 dev_err(x->phy.dev, in mxs_charger_data_contact_detect()
613 return -ENXIO; in mxs_charger_data_contact_detect()
621 struct regmap *regmap = x->regmap_anatop; in mxs_charger_primary_detection()
626 * - Do check whether a charger is connected to the USB port in mxs_charger_primary_detection()
627 * - Do not Check whether the USB plug has been in contact with in mxs_charger_primary_detection()
640 dev_dbg(x->phy.dev, "It is a standard downstream port\n"); in mxs_charger_primary_detection()
657 struct regmap *regmap = x->regmap_anatop; in mxs_charger_secondary_detection()
664 dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); in mxs_charger_secondary_detection()
667 dev_dbg(x->phy.dev, "It is a charging downstream port\n"); in mxs_charger_secondary_detection()
675 struct regmap *regmap = mxs_phy->regmap_anatop; in mxs_phy_charger_detect()
676 void __iomem *base = phy->io_priv; in mxs_phy_charger_detect()
712 struct device_node *np = pdev->dev.of_node; in mxs_phy_probe()
719 clk = devm_clk_get(&pdev->dev, NULL); in mxs_phy_probe()
721 dev_err(&pdev->dev, in mxs_phy_probe()
726 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); in mxs_phy_probe()
728 return -ENOMEM; in mxs_phy_probe()
730 /* Some SoCs don't have anatop registers */ in mxs_phy_probe()
731 if (of_property_present(np, "fsl,anatop")) { in mxs_phy_probe()
732 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle in mxs_phy_probe()
733 (np, "fsl,anatop"); in mxs_phy_probe()
734 if (IS_ERR(mxs_phy->regmap_anatop)) { in mxs_phy_probe()
735 dev_dbg(&pdev->dev, in mxs_phy_probe()
736 "failed to find regmap for anatop\n"); in mxs_phy_probe()
737 return PTR_ERR(mxs_phy->regmap_anatop); in mxs_phy_probe()
742 if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && in mxs_phy_probe()
744 /* Scale to a 4-bit value */ in mxs_phy_probe()
745 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF in mxs_phy_probe()
746 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); in mxs_phy_probe()
747 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); in mxs_phy_probe()
748 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); in mxs_phy_probe()
751 if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && in mxs_phy_probe()
753 /* Scale to a 4-bit value. */ in mxs_phy_probe()
754 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF in mxs_phy_probe()
755 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); in mxs_phy_probe()
756 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); in mxs_phy_probe()
757 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); in mxs_phy_probe()
760 if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && in mxs_phy_probe()
762 /* Scale to a 4-bit value. Round up the values and heavily in mxs_phy_probe()
765 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF in mxs_phy_probe()
766 + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) in mxs_phy_probe()
767 / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); in mxs_phy_probe()
768 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); in mxs_phy_probe()
769 mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); in mxs_phy_probe()
774 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); in mxs_phy_probe()
775 mxs_phy->port_id = ret; in mxs_phy_probe()
777 mxs_phy->phy.io_priv = base; in mxs_phy_probe()
778 mxs_phy->phy.dev = &pdev->dev; in mxs_phy_probe()
779 mxs_phy->phy.label = DRIVER_NAME; in mxs_phy_probe()
780 mxs_phy->phy.init = mxs_phy_init; in mxs_phy_probe()
781 mxs_phy->phy.shutdown = mxs_phy_shutdown; in mxs_phy_probe()
782 mxs_phy->phy.set_suspend = mxs_phy_suspend; in mxs_phy_probe()
783 mxs_phy->phy.notify_connect = mxs_phy_on_connect; in mxs_phy_probe()
784 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; in mxs_phy_probe()
785 mxs_phy->phy.type = USB_PHY_TYPE_USB2; in mxs_phy_probe()
786 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; in mxs_phy_probe()
787 mxs_phy->phy.charger_detect = mxs_phy_charger_detect; in mxs_phy_probe()
789 mxs_phy->clk = clk; in mxs_phy_probe()
790 mxs_phy->data = of_device_get_match_data(&pdev->dev); in mxs_phy_probe()
794 device_set_wakeup_capable(&pdev->dev, true); in mxs_phy_probe()
796 return usb_add_phy_dev(&mxs_phy->phy); in mxs_phy_probe()
803 usb_remove_phy(&mxs_phy->phy); in mxs_phy_remove()
811 /* If the SoCs don't have anatop, quit */ in mxs_phy_enable_ldo_in_suspend()
812 if (!mxs_phy->regmap_anatop) in mxs_phy_enable_ldo_in_suspend()
816 regmap_write(mxs_phy->regmap_anatop, reg, in mxs_phy_enable_ldo_in_suspend()
819 regmap_write(mxs_phy->regmap_anatop, in mxs_phy_enable_ldo_in_suspend()
869 MODULE_ALIAS("platform:mxs-usb-phy");