Lines Matching +full:0 +full:x17a0
10 #define PIPE_DEVEP_MASK 0x0007ff00
18 #define USBCMD 0
19 #define USBCMD_RS 0x0001 /* Run/Stop */
20 #define USBCMD_HCRESET 0x0002 /* Host reset */
21 #define USBCMD_GRESET 0x0004 /* Global reset */
22 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
23 #define USBCMD_FGR 0x0010 /* Force Global Resume */
24 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
25 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
26 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
30 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
31 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
32 #define USBSTS_RD 0x0004 /* Resume Detect */
33 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
34 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
36 #define USBSTS_HCH 0x0020 /* HC Halted */
40 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
41 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
42 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
43 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
55 #define USBPORTSC_CCS 0x0001 /* Current Connect Status
57 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
58 #define USBPORTSC_PE 0x0004 /* Port Enable */
59 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
60 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
61 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
62 #define USBPORTSC_RD 0x0040 /* Resume Detect */
63 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
64 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
65 #define USBPORTSC_PR 0x0200 /* Port Reset */
67 #define USBPORTSC_OC 0x0400 /* Over Current condition */
68 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
69 #define USBPORTSC_SUSP 0x1000 /* Suspend */
70 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
71 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
72 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
75 #define USBLEGSUP 0xc0
76 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
77 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
78 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
81 #define USBRES_INTEL 0xc4
82 #define USBPORT1EN 0x01
83 #define USBPORT2EN 0x02
85 #define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
86 #define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
87 #define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
88 #define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
89 #define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
171 short phase; /* Between 0 and period-1 */
217 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
220 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
232 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
233 #define TD_TOKEN_PID_MASK 0xFF
241 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
242 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
243 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
330 #define SKEL_UNLINK 0
473 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
493 #define PCI_VENDOR_ID_GENESYS 0x17a0
494 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083
512 #define UHCI_IN(x) 0
513 #define UHCI_OUT(x) do { } while (0)
552 #define uhci_has_pci_registers(u) ((u)->io_addr != 0)
555 #define uhci_has_pci_registers(u) 0
562 #define uhci_big_endian_mmio(u) 0
571 return 0x04; in uhci_aspeed_reg()
573 return 0x08; in uhci_aspeed_reg()
575 return 0x80; in uhci_aspeed_reg()
577 return 0x0c; in uhci_aspeed_reg()
579 return 0x84; in uhci_aspeed_reg()
581 return 0x88; in uhci_aspeed_reg()
583 return 0x8c; in uhci_aspeed_reg()
585 return 0x90; in uhci_aspeed_reg()
587 return 0x94; in uhci_aspeed_reg()
589 pr_warn("UHCI: Unsupported register 0x%02x on Aspeed\n", reg); in uhci_aspeed_reg()
591 return 0x10; in uhci_aspeed_reg()