usb/host/ehci.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (c) 2001-2002 by David Brownell
16  * To facilitate the strongest possible byte-order checking from "sparse"
46  * high-speed devices and full/low-speed devices lying behind a TT.
49 	struct usb_device	*udev;		/* access to the TT */
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92  * ehci-timer.c) in parallel with this list.
188 			the change-suspend feature turned on */
194 	/* per-HC memory pools (could be per-bus, but ...) */
236 	unsigned		has_ppcd:1; /* support per-port change bits */
261 	/* platform-specific data -- must come last */
268 	return (struct ehci_hcd *) (hcd->hcd_priv);  in hcd_to_ehci()
275 /*-------------------------------------------------------------------------*/
279 /*-------------------------------------------------------------------------*/
286  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
317 	/* the rest is HCD-private */
324 /* mask NakCnt+T in qh->hw_alt_next */
329 /*-------------------------------------------------------------------------*/
331 /* type tag from {qh,itd,sitd,fstn}->hw_next */
338  * can be used on one system with SoC EHCI controller using big-endian
339  * descriptors as well as a normal little-endian PCI EHCI controller.
371 /*-------------------------------------------------------------------------*/
376  * See Fig 3-7 "Queue Head Structure Layout".
398 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
410 	/* the rest is HCD-private */
442 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
447 /*-------------------------------------------------------------------------*/
452 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
453 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
460  * each packet is one logical usb transaction to the device (not TT),
461  * beginning at stream->next_uframe
471  * ehci_iso_stream - groups all (s)itds for this endpoint.
500 	/* this is used to initialize sITD's tt info */
504 /*-------------------------------------------------------------------------*/
508  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
519 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
528 	/* the rest is HCD-private */
539 	unsigned		index[8];	/* in urb->iso_frame_desc */
542 /*-------------------------------------------------------------------------*/
546  * siTD, aka split-transaction isochronous Transfer Descriptor
547  *       ... describe full speed iso xfers through TT in hubs
548  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
553 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
554 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
555 	__hc32			hw_uframe;		/* EHCI table 3-10 */
556 	__hc32			hw_results;		/* EHCI table 3-11 */
561 #define	SITD_STS_ERR	(1 << 6)	/* error from TT */
570 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
571 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
574 	/* the rest is HCD-private */
585 /*-------------------------------------------------------------------------*/
591  * Manages split interrupt transactions (using TT) that span frame boundaries
600 	/* the rest is HCD-private */
605 /*-------------------------------------------------------------------------*/
608  * USB-2.0 Specification Sections 11.14 and 11.18
611  * A hub can have a single TT for all its ports, or multiple TTs (one for each
612  * port).  The bandwidth and budgeting information for the full/low-speed bus
613  * below each TT is self-contained and independent of the other TTs or the
614  * high-speed bus.
618  * the best-case estimate of the number of full-speed bytes allocated to an
621  * Removal of an endpoint invalidates a TT's budget.  Instead of trying to
622  * keep an up-to-date record, we recompute the budget when it is needed.
629 	struct list_head	ps_list;	/* Items using this TT */
631 	int			tt_port;	/* TT port number */
634 /*-------------------------------------------------------------------------*/
644 /*-------------------------------------------------------------------------*/
650  * root hub. This is a non-standard feature.  Each controller will need
655 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
662 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
682 /*-------------------------------------------------------------------------*/
685 /* Some Freescale processors have an erratum in which the TT
686  * port number in the queue head was 0..N-1 instead of 1..N.
688 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
693 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
696 /* Some Freescale processors have an erratum (USB A-005275) in which
699 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
705  * Some Freescale/NXP processors have an erratum (USB A-005697)
709 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
717 	((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \
722  * little-endian format, a minority (celleb companion chip) implement
731  * as fields of a 32-bit register.
735 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
736 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
743  * Big-endian read/write functions are arch-specific.
783 	if (ehci->imx28_write_fix)  in ehci_writel()
791  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
800 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
806 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
807 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
814 /*-------------------------------------------------------------------------*/
817  * The AMCC 440EPx not only implements its EHCI registers in big-endian
820  * EHCI controllers accessed through PCI work normally (little-endian
821  * everywhere), so we won't bother supporting a BE-only mode for now.
824 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
870 /*-------------------------------------------------------------------------*/
873 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
875 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
877 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
879 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
881 /*-------------------------------------------------------------------------*/