22 #define PCI_DEVICE_ID_INTEL_CE4100_USB	0x2e70
24 #define PCI_VENDOR_ID_ASPEED		0x1a03
25 #define PCI_DEVICE_ID_ASPEED_EHCI	0x2603
28 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC		0x0939
42 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
43 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
44 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
54  * 0x84 is the offset of in/out threshold register,
59 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
60 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD	0x007f007f
86 	return 0;  in ehci_pci_reinit()
111 		if (pdev->device == 0x01b5) {  in ehci_pci_setup()
126 		case 0x003c:	/* MCP04 */  in ehci_pci_setup()
127 		case 0x005b:	/* CK804 */  in ehci_pci_setup()
128 		case 0x00d8:	/* CK8 */  in ehci_pci_setup()
129 		case 0x00e8:	/* CK8S */  in ehci_pci_setup()
130 			if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31)) < 0)  in ehci_pci_setup()
138 		case 0x0068:  in ehci_pci_setup()
139 			if (pdev->revision < 0xa4)  in ehci_pci_setup()
157 		if (pdev->device == 0x7463) {  in ehci_pci_setup()
170 		if (pdev->device == 0x7808) {  in ehci_pci_setup()
176 		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {  in ehci_pci_setup()
180 			 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes  in ehci_pci_setup()
183 			pci_read_config_byte(pdev, 0x4b, &tmp);  in ehci_pci_setup()
184 			if (tmp & 0x20)  in ehci_pci_setup()
186 			pci_write_config_byte(pdev, 0x4b, tmp | 0x20);  in ehci_pci_setup()
201 		if (pdev->device == 0x4396) {  in ehci_pci_setup()
208 		if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&  in ehci_pci_setup()
212 			pci_read_config_byte(pdev, 0x53, &tmp);  in ehci_pci_setup()
213 			pci_write_config_byte(pdev, 0x53, tmp | (1<<3));  in ehci_pci_setup()
223 		if (pdev->device == 0xa239) {  in ehci_pci_setup()
235 		if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x90)  in ehci_pci_setup()
249 			temp &= 0x1fff;  in ehci_pci_setup()
269 		ehci->need_io_watchdog = 0;  in ehci_pci_setup()
278 		case 0x0d9d:  in ehci_pci_setup()
280 			ehci->has_ppcd = 0;  in ehci_pci_setup()
289 	temp &= 0x0f;  in ehci_pci_setup()
298 		case 0x17a0:		/* GENESYS */  in ehci_pci_setup()
300 			temp |= (ehci->hcs_params & ~0xf);  in ehci_pci_setup()
309 	/* Serial Bus Release Number is at PCI 0x60 offset */  in ehci_pci_setup()
314 			 && pdev->device == 0xa239)  in ehci_pci_setup()
317 		pci_read_config_byte(pdev, 0x60, &ehci->sbrn);  in ehci_pci_setup()
327 		pci_read_config_word(pdev, 0x62, &port_wake);  in ehci_pci_setup()
328 		if (port_wake & 0x0001) {  in ehci_pci_setup()
363 	if (ehci_resume(hcd, hibernated) != 0)  in ehci_pci_resume()
365 	return 0;  in ehci_pci_resume()
398 	PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),