tty/serial/sunzilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
57 #define	RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
67 #define	RxINT_DISAB	0	/* Rx Int Disable */
68 #define	RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
69 #define	INT_ALL_Rx	0x10	/* Int on all Rx Characters or error */
70 #define	INT_ERR_Rx	0x18	/* Int on error only */
81 #define	RxENAB  	0x1	/* Rx Enable */
84 #define	RxCRC_ENAB	0x8	/* Rx CRC Enable */
87 #define	Rx5		0x0	/* Rx 5 Bits/Character */
88 #define	Rx7		0x40	/* Rx 7 Bits/Character */
89 #define	Rx6		0x80	/* Rx 6 Bits/Character */
90 #define	Rx8		0xc0	/* Rx 8 Bits/Character */
118 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
132 /* Write Register 7' (ESCC Only) */
202 #define	WR7pEN	1	/* WR7' Enable (ESCC only) */
204 #define	FIFOEN	4	/* FIFO Enable (ESCC only) */
213 #define	Rx_CH_AV	0x1	/* Rx Character Available */
224 /* Residue Data for 8 Rx bits/char programmed */
233 /* Special Rx Condition Interrupts */
235 #define	Rx_OVR		0x20	/* Rx Overrun Error */
239 /* Read Register 2 (channel b only) - Interrupt vector */
250 /* Read Register 3 (interrupt pending register) ch a only */
253 #define	CHBRxIP	0x4		/* Channel B Rx IP */
256 #define	CHARxIP	0x20		/* Channel A Rx IP */
277 #define ZS_CLEARERR(channel)    do { sbus_writeb(ERR_RES, &channel->control); \
280 #define ZS_CLEARSTAT(channel)   do { sbus_writeb(RES_EXT_INT, &channel->control); \
283 #define ZS_CLEARFIFO(channel)   do { sbus_readb(&channel->data); \
285 				     sbus_readb(&channel->data); \
287 				     sbus_readb(&channel->data); \