Lines Matching +full:uart +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0+
3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
18 * https://github.com/sifive/sifive-blocks/
20 * The SiFive UART design is not 8250-compatible. The following common
22 * - Word lengths other than 8 bits
23 * - Break handling
24 * - Parity
25 * - Flow control
26 * - Modem signals (DSR, RI, etc.)
117 #define SIFIVE_SERIAL_NAME "sifive-serial"
122 /* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
125 /* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
129 #error Driver does not support configurations with different TX, RX FIFO sizes
137 * struct sifive_serial_port - driver-specific data extension to struct uart_port
141 * @baud_rate: UART serial line rate (e.g., 115200 baud)
145 * Configuration data specific to this SiFive UART.
157 * Structure container-of macros
178 * __ssp_early_writel() - write to a SiFive serial port register (early)
191 writel_relaxed(v, port->membase + offs); in __ssp_early_writel()
195 * __ssp_early_readl() - read from a SiFive serial port register (early)
207 * Returns: the register value read from the UART.
211 return readl_relaxed(port->membase + offs); in __ssp_early_readl()
215 * __ssp_writel() - write to a SiFive serial port register
227 __ssp_early_writel(v, offs, &ssp->port); in __ssp_writel()
231 * __ssp_readl() - read from a SiFive serial port register
240 * Returns: the value of the UART register
244 return __ssp_early_readl(&ssp->port, offs); in __ssp_readl()
248 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
251 * Read the transmit FIFO "full" bit, returning a non-zero value if the
252 * TX FIFO is full, or zero if space remains. Intended to be used to prevent
253 * writes to the TX FIFO when it's full.
255 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
265 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
281 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
284 * Transfer up to a TX FIFO size's worth of characters from the Linux serial
285 * transmit buffer to the SiFive UART TX FIFO.
287 * Context: Any context. Expects @ssp->port.lock to be held by caller.
293 uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH, in __ssp_transmit_chars()
300 * __ssp_enable_txwm() - enable transmit watermark interrupts
304 * on the SiFive UART referred to by @ssp.
308 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK) in __ssp_enable_txwm()
311 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK; in __ssp_enable_txwm()
312 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_enable_txwm()
316 * __ssp_enable_rxwm() - enable receive watermark interrupts
320 * on the SiFive UART referred to by @ssp.
324 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK) in __ssp_enable_rxwm()
327 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK; in __ssp_enable_rxwm()
328 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_enable_rxwm()
332 * __ssp_disable_txwm() - disable transmit watermark interrupts
336 * on the UART referred to by @ssp.
340 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)) in __ssp_disable_txwm()
343 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK; in __ssp_disable_txwm()
344 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_disable_txwm()
348 * __ssp_disable_rxwm() - disable receive watermark interrupts
352 * on the UART referred to by @ssp.
356 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)) in __ssp_disable_rxwm()
359 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK; in __ssp_disable_rxwm()
360 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); in __ssp_disable_rxwm()
364 * __ssp_receive_char() - receive a byte from the UART
368 * Try to read a byte from the SiFive UART RX FIFO, referenced by
373 * Returns: the byte read from the UART RX FIFO.
395 * __ssp_receive_chars() - receive multiple bytes from the UART
398 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
401 * Context: Expects ssp->port.lock to be held by caller.
409 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) { in __ssp_receive_chars()
414 ssp->port.icount.rx++; in __ssp_receive_chars()
415 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL); in __ssp_receive_chars()
418 tty_flip_buffer_push(&ssp->port.state->port); in __ssp_receive_chars()
422 * __ssp_update_div() - calculate the divisor setting by the line rate
425 * Calculate the appropriate value of the clock divisor for the UART
433 div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1; in __ssp_update_div()
439 * __ssp_update_baud_rate() - set the UART "baud rate"
443 * Calculate the UART divisor value for the target bit rate @rate for the
444 * SiFive UART described by @ssp and program it into the UART. There may
446 * by the UART due to clock ratio granularity.
451 if (ssp->baud_rate == rate) in __ssp_update_baud_rate()
454 ssp->baud_rate = rate; in __ssp_update_baud_rate()
459 * __ssp_set_stop_bits() - set the number of stop bits
463 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
476 v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT; in __ssp_set_stop_bits()
481 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
484 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
524 spin_lock(&ssp->port.lock); in sifive_serial_irq()
528 spin_unlock(&ssp->port.lock); in sifive_serial_irq()
537 spin_unlock(&ssp->port.lock); in sifive_serial_irq()
567 uart_port_lock_irqsave(&ssp->port, &flags); in sifive_serial_startup()
569 uart_port_unlock_irqrestore(&ssp->port, flags); in sifive_serial_startup()
579 uart_port_lock_irqsave(&ssp->port, &flags); in sifive_serial_shutdown()
582 uart_port_unlock_irqrestore(&ssp->port, flags); in sifive_serial_shutdown()
586 * sifive_serial_clk_notifier() - clock post-rate-change notifier
591 * On the V0 SoC, the UART IP block is derived from the CPU clock source
592 * after a synchronous divide-by-two divider, so any CPU clock rate change
593 * requires the UART baud rate to be updated. This presumably corrupts any
606 * The TX watermark is always set to 1 by this driver, which in sifive_serial_clk_notifier()
607 * means that the TX busy bit will lower when there are 0 bytes in sifive_serial_clk_notifier()
608 * left in the TX queue -- in other words, when the TX FIFO is in sifive_serial_clk_notifier()
613 * On the cycle the TX FIFO goes empty there is still a full in sifive_serial_clk_notifier()
614 * UART frame left to be transmitted in the shift register. in sifive_serial_clk_notifier()
615 * The UART provides no way for software to directly determine in sifive_serial_clk_notifier()
621 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate)); in sifive_serial_clk_notifier()
624 if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) { in sifive_serial_clk_notifier()
625 ssp->port.uartclk = cnd->new_rate; in sifive_serial_clk_notifier()
642 if ((termios->c_cflag & CSIZE) != CS8) { in sifive_serial_set_termios()
643 dev_err_once(ssp->port.dev, "only 8-bit words supported\n"); in sifive_serial_set_termios()
644 termios->c_cflag &= ~CSIZE; in sifive_serial_set_termios()
645 termios->c_cflag |= CS8; in sifive_serial_set_termios()
647 if (termios->c_iflag & (INPCK | PARMRK)) in sifive_serial_set_termios()
648 dev_err_once(ssp->port.dev, "parity checking not supported\n"); in sifive_serial_set_termios()
649 if (termios->c_iflag & BRKINT) in sifive_serial_set_termios()
650 dev_err_once(ssp->port.dev, "BREAK detection not supported\n"); in sifive_serial_set_termios()
651 termios->c_iflag &= ~(INPCK|PARMRK|BRKINT); in sifive_serial_set_termios()
654 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1; in sifive_serial_set_termios()
659 ssp->port.uartclk / 16); in sifive_serial_set_termios()
662 spin_lock_irqsave(&ssp->port.lock, flags); in sifive_serial_set_termios()
664 /* Update the per-port timeout */ in sifive_serial_set_termios()
665 uart_update_timeout(port, termios->c_cflag, rate); in sifive_serial_set_termios()
667 ssp->port.read_status_mask = 0; in sifive_serial_set_termios()
672 if ((termios->c_cflag & CREAD) == 0) in sifive_serial_set_termios()
679 spin_unlock_irqrestore(&ssp->port.lock, flags); in sifive_serial_set_termios()
695 ssp->port.type = PORT_SIFIVE_V0; in sifive_serial_config_port()
701 return -EINVAL; in sifive_serial_verify_port()
706 return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL; in sifive_serial_type()
749 struct earlycon_device *dev = con->data; in early_sifive_serial_write()
750 struct uart_port *port = &dev->port; in early_sifive_serial_write()
758 struct uart_port *port = &dev->port; in early_sifive_serial_setup()
760 if (!port->membase) in early_sifive_serial_setup()
761 return -ENODEV; in early_sifive_serial_setup()
763 dev->con->write = early_sifive_serial_write; in early_sifive_serial_setup()
769 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
792 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index]; in sifive_serial_console_write()
801 if (ssp->port.sysrq) in sifive_serial_console_write()
804 locked = spin_trylock(&ssp->port.lock); in sifive_serial_console_write()
806 spin_lock(&ssp->port.lock); in sifive_serial_console_write()
811 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar); in sifive_serial_console_write()
816 spin_unlock(&ssp->port.lock); in sifive_serial_console_write()
828 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS) in sifive_serial_console_setup()
829 return -ENODEV; in sifive_serial_console_setup()
831 ssp = sifive_serial_console_ports[co->index]; in sifive_serial_console_setup()
833 return -ENODEV; in sifive_serial_console_setup()
838 return uart_set_options(&ssp->port, co, baud, parity, bits, flow); in sifive_serial_console_setup()
849 .index = -1,
863 sifive_serial_console_ports[ssp->port.line] = ssp; in __ssp_add_console_port()
868 sifive_serial_console_ports[ssp->port.line] = NULL; in __ssp_remove_console_port()
924 return -EPROBE_DEFER; in sifive_serial_probe()
930 clk = devm_clk_get_enabled(&pdev->dev, NULL); in sifive_serial_probe()
932 dev_err(&pdev->dev, "unable to find controller clock\n"); in sifive_serial_probe()
936 id = of_alias_get_id(pdev->dev.of_node, "serial"); in sifive_serial_probe()
938 dev_err(&pdev->dev, "missing aliases entry\n"); in sifive_serial_probe()
944 dev_err(&pdev->dev, "too many UARTs (%d)\n", id); in sifive_serial_probe()
945 return -EINVAL; in sifive_serial_probe()
949 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); in sifive_serial_probe()
951 return -ENOMEM; in sifive_serial_probe()
953 ssp->port.dev = &pdev->dev; in sifive_serial_probe()
954 ssp->port.type = PORT_SIFIVE_V0; in sifive_serial_probe()
955 ssp->port.iotype = UPIO_MEM; in sifive_serial_probe()
956 ssp->port.irq = irq; in sifive_serial_probe()
957 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH; in sifive_serial_probe()
958 ssp->port.ops = &sifive_serial_uops; in sifive_serial_probe()
959 ssp->port.line = id; in sifive_serial_probe()
960 ssp->port.mapbase = mem->start; in sifive_serial_probe()
961 ssp->port.membase = base; in sifive_serial_probe()
962 ssp->dev = &pdev->dev; in sifive_serial_probe()
963 ssp->clk = clk; in sifive_serial_probe()
964 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier; in sifive_serial_probe()
966 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier); in sifive_serial_probe()
968 dev_err(&pdev->dev, "could not register clock notifier: %d\n", in sifive_serial_probe()
974 ssp->port.uartclk = clk_get_rate(ssp->clk); in sifive_serial_probe()
975 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; in sifive_serial_probe()
990 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags, in sifive_serial_probe()
991 dev_name(&pdev->dev), ssp); in sifive_serial_probe()
993 dev_err(&pdev->dev, "could not attach interrupt: %d\n", r); in sifive_serial_probe()
999 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_probe()
1001 dev_err(&pdev->dev, "could not add uart: %d\n", r); in sifive_serial_probe()
1009 free_irq(ssp->port.irq, ssp); in sifive_serial_probe()
1011 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); in sifive_serial_probe()
1021 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_remove()
1022 free_irq(ssp->port.irq, ssp); in sifive_serial_remove()
1023 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); in sifive_serial_remove()
1032 return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_suspend()
1039 return uart_resume_port(&sifive_serial_uart_driver, &ssp->port); in sifive_serial_resume()
1046 { .compatible = "sifive,fu540-c000-uart0" },
1091 MODULE_DESCRIPTION("SiFive UART serial driver");