Lines Matching +full:wo +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
23 #define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */
24 #define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
32 #define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
57 * QSPI Configuration Register - Baud rate and slave select
113 * data formats
121 * struct zynq_qspi - Defines qspi driver instance
151 return readl_relaxed(xqspi->regs + offset); in zynq_qspi_read()
157 writel_relaxed(val, xqspi->regs + offset); in zynq_qspi_write()
161 * zynq_qspi_init_hw - Initialize the hardware
167 * - Master mode
168 * - Baud rate divisor is set to 2
169 * - Tx threshold set to 1l Rx threshold set to 32
170 * - Flash memory interface mode enabled
171 * - Size of the word to be transferred as 8 bit
173 * - Disable and clear all the interrupts
174 * - Enable manual slave select
175 * - Enable manual start
176 * - Deselect all the chip select lines
177 * - Set the size of the word to be transferred as 32 bit
178 * - Set the little endian mode of TX FIFO and
179 * - Enable the QSPI controller
234 if (op->addr.nbytes > 3) in zynq_qspi_supports_op()
241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer
247 u32 data; in zynq_qspi_rxfifo_op() local
249 data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET); in zynq_qspi_rxfifo_op()
251 if (xqspi->rxbuf) { in zynq_qspi_rxfifo_op()
252 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size); in zynq_qspi_rxfifo_op()
253 xqspi->rxbuf += size; in zynq_qspi_rxfifo_op()
256 xqspi->rx_bytes -= size; in zynq_qspi_rxfifo_op()
257 if (xqspi->rx_bytes < 0) in zynq_qspi_rxfifo_op()
258 xqspi->rx_bytes = 0; in zynq_qspi_rxfifo_op()
262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO
271 u32 data; in zynq_qspi_txfifo_op() local
273 if (xqspi->txbuf) { in zynq_qspi_txfifo_op()
274 data = 0xffffffff; in zynq_qspi_txfifo_op()
275 memcpy(&data, xqspi->txbuf, size); in zynq_qspi_txfifo_op()
276 xqspi->txbuf += size; in zynq_qspi_txfifo_op()
278 data = 0; in zynq_qspi_txfifo_op()
281 xqspi->tx_bytes -= size; in zynq_qspi_txfifo_op()
282 zynq_qspi_write(xqspi, offset[size - 1], data); in zynq_qspi_txfifo_op()
286 * zynq_qspi_chipselect - Select or deselect the chip select line
292 struct spi_controller *ctlr = spi->master; in zynq_qspi_chipselect()
297 if (ctlr->num_chipselect > 1) { in zynq_qspi_chipselect()
318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer
325 * Return: 0 on success and -EINVAL on invalid input parameter
342 * i.e. 000 - divide by 2 in zynq_qspi_config_op()
343 * 001 - divide by 4 in zynq_qspi_config_op()
344 * ---------------- in zynq_qspi_config_op()
345 * 111 - divide by 256 in zynq_qspi_config_op()
348 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > in zynq_qspi_config_op()
349 spi->max_speed_hz) in zynq_qspi_config_op()
357 if (spi->mode & SPI_CPHA) in zynq_qspi_config_op()
359 if (spi->mode & SPI_CPOL) in zynq_qspi_config_op()
370 * zynq_qspi_setup_op - Configure the QSPI controller
380 struct spi_controller *ctlr = spi->master; in zynq_qspi_setup_op()
384 if (ctlr->busy) in zynq_qspi_setup_op()
385 return -EBUSY; in zynq_qspi_setup_op()
387 ret = clk_enable(qspi->refclk); in zynq_qspi_setup_op()
391 ret = clk_enable(qspi->pclk); in zynq_qspi_setup_op()
393 clk_disable(qspi->refclk); in zynq_qspi_setup_op()
404 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible
414 len = xqspi->tx_bytes; in zynq_qspi_write_op()
430 if (xqspi->txbuf) { in zynq_qspi_write_op()
431 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET, in zynq_qspi_write_op()
432 xqspi->txbuf, count); in zynq_qspi_write_op()
433 xqspi->txbuf += count * 4; in zynq_qspi_write_op()
436 writel_relaxed(0, xqspi->regs + in zynq_qspi_write_op()
440 xqspi->tx_bytes -= count * 4; in zynq_qspi_write_op()
444 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible
452 len = xqspi->rx_bytes - xqspi->tx_bytes; in zynq_qspi_read_op()
456 if (xqspi->rxbuf) { in zynq_qspi_read_op()
457 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET, in zynq_qspi_read_op()
458 xqspi->rxbuf, count); in zynq_qspi_read_op()
459 xqspi->rxbuf += count * 4; in zynq_qspi_read_op()
462 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET); in zynq_qspi_read_op()
464 xqspi->rx_bytes -= count * 4; in zynq_qspi_read_op()
465 len -= count * 4; in zynq_qspi_read_op()
472 * zynq_qspi_irq - Interrupt service routine of the QSPI controller
477 * On TX empty interrupt this function reads the received data from RX FIFO and
478 * fills the TX FIFO if there is any data remaining to be transferred.
499 /* Read out the data from the RX FIFO */ in zynq_qspi_irq()
501 if (xqspi->tx_bytes) { in zynq_qspi_irq()
502 /* There is more data to send */ in zynq_qspi_irq()
510 if (!xqspi->rx_bytes) { in zynq_qspi_irq()
514 complete(&xqspi->data_completion); in zynq_qspi_irq()
524 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer
537 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->master); in zynq_qspi_exec_mem_op()
541 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", in zynq_qspi_exec_mem_op()
542 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in zynq_qspi_exec_mem_op()
543 op->dummy.buswidth, op->data.buswidth); in zynq_qspi_exec_mem_op()
545 zynq_qspi_chipselect(mem->spi, true); in zynq_qspi_exec_mem_op()
546 zynq_qspi_config_op(xqspi, mem->spi); in zynq_qspi_exec_mem_op()
548 if (op->cmd.opcode) { in zynq_qspi_exec_mem_op()
549 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
550 xqspi->txbuf = (u8 *)&op->cmd.opcode; in zynq_qspi_exec_mem_op()
551 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
552 xqspi->tx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
553 xqspi->rx_bytes = op->cmd.nbytes; in zynq_qspi_exec_mem_op()
557 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
559 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
562 if (op->addr.nbytes) { in zynq_qspi_exec_mem_op()
563 for (i = 0; i < op->addr.nbytes; i++) { in zynq_qspi_exec_mem_op()
564 xqspi->txbuf[i] = op->addr.val >> in zynq_qspi_exec_mem_op()
565 (8 * (op->addr.nbytes - i - 1)); in zynq_qspi_exec_mem_op()
568 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
569 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
570 xqspi->tx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
571 xqspi->rx_bytes = op->addr.nbytes; in zynq_qspi_exec_mem_op()
575 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
577 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
580 if (op->dummy.nbytes) { in zynq_qspi_exec_mem_op()
581 tmpbuf = kzalloc(op->dummy.nbytes, GFP_KERNEL); in zynq_qspi_exec_mem_op()
583 return -ENOMEM; in zynq_qspi_exec_mem_op()
585 memset(tmpbuf, 0xff, op->dummy.nbytes); in zynq_qspi_exec_mem_op()
586 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
587 xqspi->txbuf = tmpbuf; in zynq_qspi_exec_mem_op()
588 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
589 xqspi->tx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
590 xqspi->rx_bytes = op->dummy.nbytes; in zynq_qspi_exec_mem_op()
594 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
596 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
601 if (op->data.nbytes) { in zynq_qspi_exec_mem_op()
602 reinit_completion(&xqspi->data_completion); in zynq_qspi_exec_mem_op()
603 if (op->data.dir == SPI_MEM_DATA_OUT) { in zynq_qspi_exec_mem_op()
604 xqspi->txbuf = (u8 *)op->data.buf.out; in zynq_qspi_exec_mem_op()
605 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
606 xqspi->rxbuf = NULL; in zynq_qspi_exec_mem_op()
607 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
609 xqspi->txbuf = NULL; in zynq_qspi_exec_mem_op()
610 xqspi->rxbuf = (u8 *)op->data.buf.in; in zynq_qspi_exec_mem_op()
611 xqspi->rx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
612 xqspi->tx_bytes = op->data.nbytes; in zynq_qspi_exec_mem_op()
618 if (!wait_for_completion_timeout(&xqspi->data_completion, in zynq_qspi_exec_mem_op()
620 err = -ETIMEDOUT; in zynq_qspi_exec_mem_op()
622 zynq_qspi_chipselect(mem->spi, false); in zynq_qspi_exec_mem_op()
633 * zynq_qspi_probe - Probe method for the QSPI driver
636 * This function initializes the driver data structures and the hardware.
644 struct device *dev = &pdev->dev; in zynq_qspi_probe()
645 struct device_node *np = dev->of_node; in zynq_qspi_probe()
649 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); in zynq_qspi_probe()
651 return -ENOMEM; in zynq_qspi_probe()
654 xqspi->dev = dev; in zynq_qspi_probe()
656 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); in zynq_qspi_probe()
657 if (IS_ERR(xqspi->regs)) { in zynq_qspi_probe()
658 ret = PTR_ERR(xqspi->regs); in zynq_qspi_probe()
662 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); in zynq_qspi_probe()
663 if (IS_ERR(xqspi->pclk)) { in zynq_qspi_probe()
664 dev_err(&pdev->dev, "pclk clock not found.\n"); in zynq_qspi_probe()
665 ret = PTR_ERR(xqspi->pclk); in zynq_qspi_probe()
669 init_completion(&xqspi->data_completion); in zynq_qspi_probe()
671 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); in zynq_qspi_probe()
672 if (IS_ERR(xqspi->refclk)) { in zynq_qspi_probe()
673 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in zynq_qspi_probe()
674 ret = PTR_ERR(xqspi->refclk); in zynq_qspi_probe()
678 ret = clk_prepare_enable(xqspi->pclk); in zynq_qspi_probe()
680 dev_err(&pdev->dev, "Unable to enable APB clock.\n"); in zynq_qspi_probe()
684 ret = clk_prepare_enable(xqspi->refclk); in zynq_qspi_probe()
686 dev_err(&pdev->dev, "Unable to enable device clock.\n"); in zynq_qspi_probe()
690 xqspi->irq = platform_get_irq(pdev, 0); in zynq_qspi_probe()
691 if (xqspi->irq < 0) { in zynq_qspi_probe()
692 ret = xqspi->irq; in zynq_qspi_probe()
695 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, in zynq_qspi_probe()
696 0, pdev->name, xqspi); in zynq_qspi_probe()
698 ret = -ENXIO; in zynq_qspi_probe()
699 dev_err(&pdev->dev, "request_irq failed\n"); in zynq_qspi_probe()
703 ret = of_property_read_u32(np, "num-cs", in zynq_qspi_probe()
706 ctlr->num_chipselect = 1; in zynq_qspi_probe()
708 ret = -EINVAL; in zynq_qspi_probe()
709 dev_err(&pdev->dev, "only 2 chip selects are available\n"); in zynq_qspi_probe()
712 ctlr->num_chipselect = num_cs; in zynq_qspi_probe()
715 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | in zynq_qspi_probe()
717 ctlr->mem_ops = &zynq_qspi_mem_ops; in zynq_qspi_probe()
718 ctlr->setup = zynq_qspi_setup_op; in zynq_qspi_probe()
719 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; in zynq_qspi_probe()
720 ctlr->dev.of_node = np; in zynq_qspi_probe()
723 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect); in zynq_qspi_probe()
725 ret = devm_spi_register_controller(&pdev->dev, ctlr); in zynq_qspi_probe()
727 dev_err(&pdev->dev, "spi_register_master failed\n"); in zynq_qspi_probe()
734 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_probe()
736 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_probe()
744 * zynq_qspi_remove - Remove method for the QSPI driver
759 clk_disable_unprepare(xqspi->refclk); in zynq_qspi_remove()
760 clk_disable_unprepare(xqspi->pclk); in zynq_qspi_remove()
764 { .compatible = "xlnx,zynq-qspi-1.0", },
771 * zynq_qspi_driver - This structure defines the QSPI platform driver
777 .name = "zynq-qspi",