Lines Matching +full:spi +full:- +full:lsb +full:- +full:first
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale SPI controller driver.
10 * CPM SPI and QE buffer descriptors mode support:
19 #include <linux/dma-mapping.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
66 .compatible = "fsl,spi",
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
89 static void fsl_spi_change_mode(struct spi_device *spi) in fsl_spi_change_mode() argument
91 struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller); in fsl_spi_change_mode()
92 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_change_mode()
93 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_change_mode()
94 __be32 __iomem *mode = ®_base->mode; in fsl_spi_change_mode()
97 if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) in fsl_spi_change_mode()
100 /* Turn off IRQs locally to minimize time that SPI is disabled. */ in fsl_spi_change_mode()
103 /* Turn off SPI unit prior changing mode */ in fsl_spi_change_mode()
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); in fsl_spi_change_mode()
107 if (mspi->flags & SPI_CPM_MODE) { in fsl_spi_change_mode()
110 mpc8xxx_spi_write_reg(mode, cs->hw_mode); in fsl_spi_change_mode()
140 *rx_shift = 16; /* LSB in bit 16 */ in fsl_spi_grlib_set_shifts()
141 *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */ in fsl_spi_grlib_set_shifts()
143 *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */ in fsl_spi_grlib_set_shifts()
149 struct spi_device *spi, in mspi_apply_cpu_mode_quirks() argument
153 cs->rx_shift = 0; in mspi_apply_cpu_mode_quirks()
154 cs->tx_shift = 0; in mspi_apply_cpu_mode_quirks()
156 cs->get_rx = mpc8xxx_spi_rx_buf_u8; in mspi_apply_cpu_mode_quirks()
157 cs->get_tx = mpc8xxx_spi_tx_buf_u8; in mspi_apply_cpu_mode_quirks()
159 cs->get_rx = mpc8xxx_spi_rx_buf_u16; in mspi_apply_cpu_mode_quirks()
160 cs->get_tx = mpc8xxx_spi_tx_buf_u16; in mspi_apply_cpu_mode_quirks()
162 cs->get_rx = mpc8xxx_spi_rx_buf_u32; in mspi_apply_cpu_mode_quirks()
163 cs->get_tx = mpc8xxx_spi_tx_buf_u32; in mspi_apply_cpu_mode_quirks()
166 if (mpc8xxx_spi->set_shifts) in mspi_apply_cpu_mode_quirks()
167 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, in mspi_apply_cpu_mode_quirks()
169 !(spi->mode & SPI_LSB_FIRST)); in mspi_apply_cpu_mode_quirks()
171 mpc8xxx_spi->rx_shift = cs->rx_shift; in mspi_apply_cpu_mode_quirks()
172 mpc8xxx_spi->tx_shift = cs->tx_shift; in mspi_apply_cpu_mode_quirks()
173 mpc8xxx_spi->get_rx = cs->get_rx; in mspi_apply_cpu_mode_quirks()
174 mpc8xxx_spi->get_tx = cs->get_tx; in mspi_apply_cpu_mode_quirks()
177 static int fsl_spi_setup_transfer(struct spi_device *spi, in fsl_spi_setup_transfer() argument
184 struct spi_mpc8xxx_cs *cs = spi->controller_state; in fsl_spi_setup_transfer()
186 mpc8xxx_spi = spi_controller_get_devdata(spi->controller); in fsl_spi_setup_transfer()
189 bits_per_word = t->bits_per_word; in fsl_spi_setup_transfer()
190 hz = t->speed_hz; in fsl_spi_setup_transfer()
193 /* spi_transfer level calls that work per-word */ in fsl_spi_setup_transfer()
195 bits_per_word = spi->bits_per_word; in fsl_spi_setup_transfer()
198 hz = spi->max_speed_hz; in fsl_spi_setup_transfer()
200 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) in fsl_spi_setup_transfer()
201 mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word); in fsl_spi_setup_transfer()
206 bits_per_word = bits_per_word - 1; in fsl_spi_setup_transfer()
209 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 in fsl_spi_setup_transfer()
212 cs->hw_mode |= SPMODE_LEN(bits_per_word); in fsl_spi_setup_transfer()
214 if ((mpc8xxx_spi->spibrg / hz) > 64) { in fsl_spi_setup_transfer()
215 cs->hw_mode |= SPMODE_DIV16; in fsl_spi_setup_transfer()
216 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; in fsl_spi_setup_transfer()
219 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024); in fsl_spi_setup_transfer()
223 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; in fsl_spi_setup_transfer()
226 pm--; in fsl_spi_setup_transfer()
228 cs->hw_mode |= SPMODE_PM(pm); in fsl_spi_setup_transfer()
230 fsl_spi_change_mode(spi); in fsl_spi_setup_transfer()
238 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs()
240 mspi->count = len; in fsl_spi_cpu_bufs()
243 mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
246 word = mspi->get_tx(mspi); in fsl_spi_cpu_bufs()
247 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_bufs()
252 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, in fsl_spi_bufs() argument
255 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller); in fsl_spi_bufs()
257 unsigned int len = t->len; in fsl_spi_bufs()
261 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
262 bits_per_word = spi->bits_per_word; in fsl_spi_bufs()
263 if (t->bits_per_word) in fsl_spi_bufs()
264 bits_per_word = t->bits_per_word; in fsl_spi_bufs()
271 mpc8xxx_spi->tx = t->tx_buf; in fsl_spi_bufs()
272 mpc8xxx_spi->rx = t->rx_buf; in fsl_spi_bufs()
274 reinit_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
276 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
283 wait_for_completion(&mpc8xxx_spi->done); in fsl_spi_bufs()
286 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_bufs()
288 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_bufs()
291 return mpc8xxx_spi->count; in fsl_spi_bufs()
299 struct spi_transfer *first; in fsl_spi_prepare_message() local
301 first = list_first_entry(&m->transfers, struct spi_transfer, in fsl_spi_prepare_message()
308 * Some glitches can appear on the SPI clock when the mode changes. in fsl_spi_prepare_message()
310 * now to change the mode without having a chip-select asserted. in fsl_spi_prepare_message()
312 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_spi_prepare_message()
313 if (t->speed_hz != first->speed_hz) { in fsl_spi_prepare_message()
314 dev_err(&m->spi->dev, in fsl_spi_prepare_message()
316 return -EINVAL; in fsl_spi_prepare_message()
318 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { in fsl_spi_prepare_message()
319 if (t->len < 256 || t->bits_per_word != 8) in fsl_spi_prepare_message()
321 if ((t->len & 3) == 0) in fsl_spi_prepare_message()
322 t->bits_per_word = 32; in fsl_spi_prepare_message()
323 else if ((t->len & 1) == 0) in fsl_spi_prepare_message()
324 t->bits_per_word = 16; in fsl_spi_prepare_message()
329 * Unfortnatly that doesn't work for LSB so in fsl_spi_prepare_message()
331 * Note: 32 bits word, LSB works iff in fsl_spi_prepare_message()
334 if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) in fsl_spi_prepare_message()
335 return -EINVAL; in fsl_spi_prepare_message()
336 if (t->bits_per_word == 16 || t->bits_per_word == 32) in fsl_spi_prepare_message()
337 t->bits_per_word = 8; /* pretend its 8 bits */ in fsl_spi_prepare_message()
338 if (t->bits_per_word == 8 && t->len >= 256 && in fsl_spi_prepare_message()
339 (mpc8xxx_spi->flags & SPI_CPM1)) in fsl_spi_prepare_message()
340 t->bits_per_word = 16; in fsl_spi_prepare_message()
343 return fsl_spi_setup_transfer(m->spi, first); in fsl_spi_prepare_message()
347 struct spi_device *spi, in fsl_spi_transfer_one() argument
352 status = fsl_spi_setup_transfer(spi, t); in fsl_spi_transfer_one()
355 if (t->len) in fsl_spi_transfer_one()
356 status = fsl_spi_bufs(spi, t, !!t->tx_dma || !!t->rx_dma); in fsl_spi_transfer_one()
358 return -EMSGSIZE; in fsl_spi_transfer_one()
366 return fsl_spi_setup_transfer(msg->spi, NULL); in fsl_spi_unprepare_message()
369 static int fsl_spi_setup(struct spi_device *spi) in fsl_spi_setup() argument
376 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); in fsl_spi_setup()
378 if (!spi->max_speed_hz) in fsl_spi_setup()
379 return -EINVAL; in fsl_spi_setup()
384 return -ENOMEM; in fsl_spi_setup()
385 spi_set_ctldata(spi, cs); in fsl_spi_setup()
388 mpc8xxx_spi = spi_controller_get_devdata(spi->controller); in fsl_spi_setup()
390 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
392 hw_mode = cs->hw_mode; /* Save original settings */ in fsl_spi_setup()
393 cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); in fsl_spi_setup()
395 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH in fsl_spi_setup()
398 if (spi->mode & SPI_CPHA) in fsl_spi_setup()
399 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; in fsl_spi_setup()
400 if (spi->mode & SPI_CPOL) in fsl_spi_setup()
401 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; in fsl_spi_setup()
402 if (!(spi->mode & SPI_LSB_FIRST)) in fsl_spi_setup()
403 cs->hw_mode |= SPMODE_REV; in fsl_spi_setup()
404 if (spi->mode & SPI_LOOP) in fsl_spi_setup()
405 cs->hw_mode |= SPMODE_LOOP; in fsl_spi_setup()
407 retval = fsl_spi_setup_transfer(spi, NULL); in fsl_spi_setup()
409 cs->hw_mode = hw_mode; /* Restore settings */ in fsl_spi_setup()
418 static void fsl_spi_cleanup(struct spi_device *spi) in fsl_spi_cleanup() argument
420 struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi); in fsl_spi_cleanup()
423 spi_set_ctldata(spi, NULL); in fsl_spi_cleanup()
428 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_cpu_irq()
430 /* We need handle RX first */ in fsl_spi_cpu_irq()
432 u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); in fsl_spi_cpu_irq()
434 if (mspi->rx) in fsl_spi_cpu_irq()
435 mspi->get_rx(rx_data, mspi); in fsl_spi_cpu_irq()
441 mpc8xxx_spi_read_reg(®_base->event)) & in fsl_spi_cpu_irq()
446 mpc8xxx_spi_write_reg(®_base->event, events); in fsl_spi_cpu_irq()
448 mspi->count -= 1; in fsl_spi_cpu_irq()
449 if (mspi->count) { in fsl_spi_cpu_irq()
450 u32 word = mspi->get_tx(mspi); in fsl_spi_cpu_irq()
452 mpc8xxx_spi_write_reg(®_base->transmit, word); in fsl_spi_cpu_irq()
454 complete(&mspi->done); in fsl_spi_cpu_irq()
463 struct fsl_spi_reg __iomem *reg_base = mspi->reg_base; in fsl_spi_irq()
466 events = mpc8xxx_spi_read_reg(®_base->event); in fsl_spi_irq()
470 dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); in fsl_spi_irq()
472 if (mspi->flags & SPI_CPM_MODE) in fsl_spi_irq()
480 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on) in fsl_spi_grlib_cs_control() argument
482 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller); in fsl_spi_grlib_cs_control()
483 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_cs_control()
485 u16 cs = spi_get_chipselect(spi, 0); in fsl_spi_grlib_cs_control()
487 if (cs < mpc8xxx_spi->native_chipselects) { in fsl_spi_grlib_cs_control()
488 slvsel = mpc8xxx_spi_read_reg(®_base->slvsel); in fsl_spi_grlib_cs_control()
490 mpc8xxx_spi_write_reg(®_base->slvsel, slvsel); in fsl_spi_grlib_cs_control()
498 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base; in fsl_spi_grlib_probe()
502 capabilities = mpc8xxx_spi_read_reg(®_base->cap); in fsl_spi_grlib_probe()
504 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts; in fsl_spi_grlib_probe()
507 mpc8xxx_spi->max_bits_per_word = mbits + 1; in fsl_spi_grlib_probe()
509 mpc8xxx_spi->native_chipselects = 0; in fsl_spi_grlib_probe()
511 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities); in fsl_spi_grlib_probe()
512 mpc8xxx_spi_write_reg(®_base->slvsel, 0xffffffff); in fsl_spi_grlib_probe()
514 host->num_chipselect = mpc8xxx_spi->native_chipselects; in fsl_spi_grlib_probe()
515 host->set_cs = fsl_spi_grlib_cs_control; in fsl_spi_grlib_probe()
518 static void fsl_spi_cs_control(struct spi_device *spi, bool on) in fsl_spi_cs_control() argument
520 struct device *dev = spi->dev.parent->parent; in fsl_spi_cs_control()
524 if (WARN_ON_ONCE(!pinfo->immr_spi_cs)) in fsl_spi_cs_control()
526 iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs); in fsl_spi_cs_control()
541 ret = -ENOMEM; in fsl_spi_probe()
549 host->setup = fsl_spi_setup; in fsl_spi_probe()
550 host->cleanup = fsl_spi_cleanup; in fsl_spi_probe()
551 host->prepare_message = fsl_spi_prepare_message; in fsl_spi_probe()
552 host->transfer_one = fsl_spi_transfer_one; in fsl_spi_probe()
553 host->unprepare_message = fsl_spi_unprepare_message; in fsl_spi_probe()
554 host->use_gpio_descriptors = true; in fsl_spi_probe()
555 host->set_cs = fsl_spi_cs_control; in fsl_spi_probe()
558 mpc8xxx_spi->max_bits_per_word = 32; in fsl_spi_probe()
559 mpc8xxx_spi->type = fsl_spi_get_type(dev); in fsl_spi_probe()
565 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem); in fsl_spi_probe()
566 if (IS_ERR(mpc8xxx_spi->reg_base)) { in fsl_spi_probe()
567 ret = PTR_ERR(mpc8xxx_spi->reg_base); in fsl_spi_probe()
571 if (mpc8xxx_spi->type == TYPE_GRLIB) in fsl_spi_probe()
574 if (mpc8xxx_spi->flags & SPI_CPM_MODE) in fsl_spi_probe()
575 host->bits_per_word_mask = in fsl_spi_probe()
578 host->bits_per_word_mask = in fsl_spi_probe()
581 host->bits_per_word_mask &= in fsl_spi_probe()
582 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); in fsl_spi_probe()
584 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
585 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; in fsl_spi_probe()
587 if (mpc8xxx_spi->set_shifts) in fsl_spi_probe()
588 /* 8 bits per word and MSB first */ in fsl_spi_probe()
589 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, in fsl_spi_probe()
590 &mpc8xxx_spi->tx_shift, 8, 1); in fsl_spi_probe()
592 /* Register for SPI Interrupt */ in fsl_spi_probe()
593 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq, in fsl_spi_probe()
599 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_probe()
601 /* SPI controller initializations */ in fsl_spi_probe()
602 mpc8xxx_spi_write_reg(®_base->mode, 0); in fsl_spi_probe()
603 mpc8xxx_spi_write_reg(®_base->mask, 0); in fsl_spi_probe()
604 mpc8xxx_spi_write_reg(®_base->command, 0); in fsl_spi_probe()
605 mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); in fsl_spi_probe()
607 /* Enable SPI interface */ in fsl_spi_probe()
608 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; in fsl_spi_probe()
609 if (mpc8xxx_spi->max_bits_per_word < 8) { in fsl_spi_probe()
611 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1); in fsl_spi_probe()
613 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) in fsl_spi_probe()
616 mpc8xxx_spi_write_reg(®_base->mode, regval); in fsl_spi_probe()
623 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); in fsl_spi_probe()
637 struct device *dev = &ofdev->dev; in of_fsl_spi_probe()
638 struct device_node *np = ofdev->dev.of_node; in of_fsl_spi_probe()
653 type = fsl_spi_get_type(&ofdev->dev); in of_fsl_spi_probe()
661 pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4); in of_fsl_spi_probe()
662 if (!pinfo->immr_spi_cs) in of_fsl_spi_probe()
663 return -ENOMEM; in of_fsl_spi_probe()
668 * device on the first "chipselect". Else we let the core code in of_fsl_spi_probe()
677 pdata->max_chipselect = 1; in of_fsl_spi_probe()
679 pdata->max_chipselect = ret + spisel_boot; in of_fsl_spi_probe()
699 iounmap(pinfo->immr_spi_cs); in of_fsl_spi_probe()
724 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
725 * only. The driver should go away soon, since newer MPC8323E-RDB's device
735 if (!dev_get_platdata(&pdev->dev)) in plat_mpc8xxx_spi_probe()
736 return -EINVAL; in plat_mpc8xxx_spi_probe()
740 return -EINVAL; in plat_mpc8xxx_spi_probe()
746 host = fsl_spi_probe(&pdev->dev, mem, irq); in plat_mpc8xxx_spi_probe()
800 MODULE_DESCRIPTION("Simple Freescale SPI Driver");