Lines Matching +full:wo +full:- +full:data
4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
62 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
69 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
76 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \
142 * Returned to data phase
143 * that requires data
187 * A command with a non-zero
213 access_mode WO
247 access_mode WO
326 access_mode WO
424 * Data FIFO Control
453 field DPARCKEN 0x40 /* Data Parity Check Enable */
462 * Data FIFO Status
482 access_mode WO
513 * Data Channel Host Address
545 * Data Channel Host Count
617 * Data FIFO Threshold
669 * ROM Data
677 * Data Channel Receive Message 0
725 * Data Channel Receive Message 1
770 * Data Channel Receive Message 2
809 * Data Channel Receive Message 3
839 * PCI-X Control
875 * Data Channel Sequencer Byte Count
885 * Data Channel Split Status 0
938 * Data Channel Split Status 1
1136 * Data FIFO 0 PCI Status
1155 * Data FIFO 1 PCI Status
1296 * Data Length Pointer
1297 * SCB offset for the 4 byte data length field in target mode.
1681 * Data Length Counters
1692 * Data FIFO Status
1821 * SCSI Data 0 Image
1830 * SCSI Latched Data
1841 * SCSI Data Bus
1934 access_mode WO
1988 access_mode WO
2025 access_mode WO
2117 access_mode WO
2169 access_mode WO
2236 access_mode WO
2277 access_mode WO
2323 access_mode WO
2405 * Data FIFO SCSI Transfer Control
2466 access_mode WO
2506 * Data FIFO Status
2516 field DLZERO 0x04 /* FIFO data ends on packet boundary. */
2543 * Data FIFO Queue Tag
2564 * SCSI I/O Cell Power-down Control
2587 * Data Group CRC Interval.
2597 * Data Transfer Negotiation Address
2607 * Data Transfer Negotiation Data - Period Byte
2628 * Data Transfer Negotiation Data - Offset Byte
2639 * Data Transfer Negotiation Data - PPR Options
2654 * Data Transfer Negotiation Data - Connection Options
2725 * Negotiation Table Annex Data Port.
2747 * 960MHz Phase-Locked Loop Control 0
2774 * 960MHz Phase-Locked Loop Control 1
2815 * 960-MHz Phase-Locked Loop Test Count
2825 * 400-MHz Phase-Locked Loop Control 0
2851 * 400-MHz Phase-Locked Loop Control 1
2873 * 400-MHz Phase-Locked Loop Test Count
2906 * SCB-Next Address Snooping logic. When an SCB is transferred to
2942 * CMC SCB Ram Back-up Address Pointer
2998 * CMC SG RAM Data Port
3008 * CMC SCB RAM Data Port
3049 * Flex DMA Data Port
3058 * Board Data
3097 * Serial EEPROM Data
3167 * Data FIFO Write Address
3168 * Pointer to the next QWD location to be written to the data FIFO.
3191 * DSP Data Channel Control
3206 * Data FIFO Read Address
3207 * Pointer to the next QWD location to be read from the data FIFO.
3239 * Data FIFO Data
3240 * Read/Write byte port into the data FIFO. The read and write
3271 access_mode WO
3289 access_mode WO
3305 * Data FIFO Pointers
3325 * Data FIFO Backup Read Pointer
3326 * Contains the data FIFO address to be restored if the last
3327 * data accessed from the data FIFO was not transferred successfully.
3346 * Data FIFO Debug Control
3361 * Data FIFO Space Count
3372 * Data FIFO Byte Count
3454 * Sequencer RAM Data Port
3560 access_mode WO
3583 access_mode WO
3590 * (0-7 only) to the top nibble and retrieve the bit indexed by that value
3669 /* ---------------------- Scratch RAM Offsets ------------------------- */
3694 * the current data phase is odd.
3722 * Per "other-id" execution queues. We use an array of
3723 * tail pointers into lists of SCBs sorted by "other-id".
3792 * Counting semaphore to prevent new select-outs
3827 field DIRECTION 0x04 /* Set indicates PCI->SCSI */
3902 * Base address of our shared data with the kernel driver in host
4014 * Number of commands "in-flight".
4038 * Target-mode CDB type to CDB length table used
4039 * in non-packetized operation.
4141 * Overloaded field for non-packetized
4163 * the data address.