94 static bool xilinx_timer_pwm_enabled(u32 tcsr0, u32 tcsr1)  in xilinx_timer_pwm_enabled()  argument
96 	return ((TCSR_PWM_MASK | TCSR_CASC) & tcsr0) == TCSR_PWM_SET &&  in xilinx_timer_pwm_enabled()
104 	u32 tlr0, tlr1, tcsr0, tcsr1;  in xilinx_pwm_apply()  local
142 	regmap_read(priv->map, TCSR0, &tcsr0);  in xilinx_pwm_apply()
144 	tlr0 = xilinx_timer_tlr_cycles(priv, tcsr0, period_cycles);  in xilinx_pwm_apply()
154 		if (!xilinx_timer_pwm_enabled(tcsr0, tcsr1)) {  in xilinx_pwm_apply()
156 			regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD);  in xilinx_pwm_apply()
159 			tcsr0 = (TCSR_PWM_SET & ~TCSR_ENT) | (tcsr0 & TCSR_UDT);  in xilinx_pwm_apply()
161 			regmap_write(priv->map, TCSR0, tcsr0);  in xilinx_pwm_apply()
177 	u32 tlr0, tlr1, tcsr0, tcsr1;  in xilinx_pwm_get_state()  local
181 	regmap_read(priv->map, TCSR0, &tcsr0);  in xilinx_pwm_get_state()
183 	state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);  in xilinx_pwm_get_state()
185 	state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);  in xilinx_pwm_get_state()