1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * drivers/pwm/pwm-tegra.c
5  * Tegra pulse-width-modulation controller driver
7  * Copyright (c) 2010-2020, NVIDIA Corporation.
8  * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11  * 1. 13-bit: Frequency division (SCALE)
12  * 2. 8-bit : Pulse division (DUTY)
13  * 3. 1-bit : Enable bit
15  * The PWM clock frequency is divided by 256 before subdividing it based
17  * frequency for PWM output. The maximum output frequency that can be
21  * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
23  * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
28  * -	When PWM is disabled, the output is driven to inactive.
29  * -	It does not allow the current PWM period to complete and
32  * -	If the register is reconfigured while PWM is running,
35  * -	If the user input duty is beyond acceptible limits,
36  *	-EINVAL is returned.
39 #include <linux/clk.h>
45 #include <linux/pwm.h>
71 	struct clk *clk;  member
89 	return readl(pc->regs + (offset << 4));  in pwm_readl()
94 	writel(value, pc->regs + (offset << 4));  in pwm_writel()
97 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,  in tegra_pwm_config()  argument
119 	if (period_ns < pc->min_period_ns)  in tegra_pwm_config()
120 		return -EINVAL;  in tegra_pwm_config()
124 	 * cycles at the PWM clock rate will take period_ns nanoseconds.  in tegra_pwm_config()
126 	 * num_channels: If single instance of PWM controller has multiple  in tegra_pwm_config()
131 	 * If every PWM controller instance has one channel respectively, i.e.  in tegra_pwm_config()
135 	if (pc->soc->num_channels == 1) {  in tegra_pwm_config()
144 		 * source clock rate as required_clk_rate, PWM controller will  in tegra_pwm_config()
150 		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))  in tegra_pwm_config()
161 		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);  in tegra_pwm_config()
163 			return -EINVAL;  in tegra_pwm_config()
166 		pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_config()
170 	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,  in tegra_pwm_config()
174 	 * Since the actual PWM divider is the register's frequency divider  in tegra_pwm_config()
179 		rate--;  in tegra_pwm_config()
181 		return -EINVAL;  in tegra_pwm_config()
188 		return -EINVAL;  in tegra_pwm_config()
193 	 * If the PWM channel is disabled, make sure to turn on the clock  in tegra_pwm_config()
196 	if (!pwm_is_enabled(pwm)) {  in tegra_pwm_config()
197 		err = pm_runtime_resume_and_get(pc->dev);  in tegra_pwm_config()
203 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_config()
206 	 * If the PWM is not enabled, turn the clock off again to save power.  in tegra_pwm_config()
208 	if (!pwm_is_enabled(pwm))  in tegra_pwm_config()
209 		pm_runtime_put(pc->dev);  in tegra_pwm_config()
214 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)  in tegra_pwm_enable()  argument
220 	rc = pm_runtime_resume_and_get(pc->dev);  in tegra_pwm_enable()
224 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_enable()
226 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_enable()
231 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)  in tegra_pwm_disable()  argument
236 	val = pwm_readl(pc, pwm->hwpwm);  in tegra_pwm_disable()
238 	pwm_writel(pc, pwm->hwpwm, val);  in tegra_pwm_disable()
240 	pm_runtime_put_sync(pc->dev);  in tegra_pwm_disable()
243 static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in tegra_pwm_apply()  argument
247 	bool enabled = pwm->state.enabled;  in tegra_pwm_apply()
249 	if (state->polarity != PWM_POLARITY_NORMAL)  in tegra_pwm_apply()
250 		return -EINVAL;  in tegra_pwm_apply()
252 	if (!state->enabled) {  in tegra_pwm_apply()
254 			tegra_pwm_disable(chip, pwm);  in tegra_pwm_apply()
259 	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);  in tegra_pwm_apply()
264 		err = tegra_pwm_enable(chip, pwm);  in tegra_pwm_apply()
279 	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);  in tegra_pwm_probe()
281 		return -ENOMEM;  in tegra_pwm_probe()
283 	pc->soc = of_device_get_match_data(&pdev->dev);  in tegra_pwm_probe()
284 	pc->dev = &pdev->dev;  in tegra_pwm_probe()
286 	pc->regs = devm_platform_ioremap_resource(pdev, 0);  in tegra_pwm_probe()
287 	if (IS_ERR(pc->regs))  in tegra_pwm_probe()
288 		return PTR_ERR(pc->regs);  in tegra_pwm_probe()
292 	pc->clk = devm_clk_get(&pdev->dev, NULL);  in tegra_pwm_probe()
293 	if (IS_ERR(pc->clk))  in tegra_pwm_probe()
294 		return PTR_ERR(pc->clk);  in tegra_pwm_probe()
296 	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);  in tegra_pwm_probe()
300 	pm_runtime_enable(&pdev->dev);  in tegra_pwm_probe()
301 	ret = pm_runtime_resume_and_get(&pdev->dev);  in tegra_pwm_probe()
306 	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);  in tegra_pwm_probe()
308 		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);  in tegra_pwm_probe()
315 	 * so that PWM period can be calculated more accurately.  in tegra_pwm_probe()
317 	pc->clk_rate = clk_get_rate(pc->clk);  in tegra_pwm_probe()
319 	/* Set minimum limit of PWM period for the IP */  in tegra_pwm_probe()
320 	pc->min_period_ns =  in tegra_pwm_probe()
321 	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;  in tegra_pwm_probe()
323 	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");  in tegra_pwm_probe()
324 	if (IS_ERR(pc->rst)) {  in tegra_pwm_probe()
325 		ret = PTR_ERR(pc->rst);  in tegra_pwm_probe()
326 		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);  in tegra_pwm_probe()
330 	reset_control_deassert(pc->rst);  in tegra_pwm_probe()
332 	pc->chip.dev = &pdev->dev;  in tegra_pwm_probe()
333 	pc->chip.ops = &tegra_pwm_ops;  in tegra_pwm_probe()
334 	pc->chip.npwm = pc->soc->num_channels;  in tegra_pwm_probe()
336 	ret = pwmchip_add(&pc->chip);  in tegra_pwm_probe()
338 		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);  in tegra_pwm_probe()
339 		reset_control_assert(pc->rst);  in tegra_pwm_probe()
343 	pm_runtime_put(&pdev->dev);  in tegra_pwm_probe()
347 	pm_runtime_put_sync_suspend(&pdev->dev);  in tegra_pwm_probe()
348 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_probe()
356 	pwmchip_remove(&pc->chip);  in tegra_pwm_remove()
358 	reset_control_assert(pc->rst);  in tegra_pwm_remove()
360 	pm_runtime_force_suspend(&pdev->dev);  in tegra_pwm_remove()
368 	clk_disable_unprepare(pc->clk);  in tegra_pwm_runtime_suspend()
372 		clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_suspend()
388 	err = clk_prepare_enable(pc->clk);  in tegra_pwm_runtime_resume()
413 	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
414 	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
415 	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
429 		.name = "tegra-pwm",
441 MODULE_DESCRIPTION("Tegra PWM controller driver");
442 MODULE_ALIAS("platform:tegra-pwm");