Lines Matching +full:bypass +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
101 return readl(chip->base + offset); in sun4i_pwm_readl()
107 writel(val, chip->base + offset); in sun4i_pwm_writel()
119 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
121 return -EINVAL; in sun4i_pwm_get_state()
126 * PWM chapter in H6 manual has a diagram which explains that if bypass in sun4i_pwm_get_state()
128 * proved that also enable bit is ignored in this case. in sun4i_pwm_get_state()
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
131 sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_get_state()
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); in sun4i_pwm_get_state()
134 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
135 state->enabled = true; in sun4i_pwm_get_state()
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
140 sun4i_pwm->data->has_prescaler_bypass) in sun4i_pwm_get_state()
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
146 return -EINVAL; in sun4i_pwm_get_state()
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
149 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
151 state->polarity = PWM_POLARITY_INVERSED; in sun4i_pwm_get_state()
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
155 state->enabled = true; in sun4i_pwm_get_state()
157 state->enabled = false; in sun4i_pwm_get_state()
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
173 bool *bypass) in sun4i_pwm_calculate() argument
178 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
180 *bypass = sun4i_pwm->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
181 state->enabled && in sun4i_pwm_calculate()
182 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
183 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
184 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); in sun4i_pwm_calculate()
186 /* Skip calculation of other parameters if we bypass them */ in sun4i_pwm_calculate()
187 if (*bypass) in sun4i_pwm_calculate()
190 if (sun4i_pwm->data->has_prescaler_bypass) { in sun4i_pwm_calculate()
198 div = clk_rate * state->period + NSEC_PER_SEC / 2; in sun4i_pwm_calculate()
200 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
214 div = div * state->period; in sun4i_pwm_calculate()
216 if (div - 1 <= PWM_PRD_MASK) in sun4i_pwm_calculate()
220 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
221 return -EINVAL; in sun4i_pwm_calculate()
225 div *= state->duty_cycle; in sun4i_pwm_calculate()
226 do_div(div, state->period); in sun4i_pwm_calculate()
241 bool bypass; in sun4i_pwm_apply() local
246 ret = clk_prepare_enable(sun4i_pwm->clk); in sun4i_pwm_apply()
248 dev_err(chip->dev, "failed to enable PWM clock\n"); in sun4i_pwm_apply()
254 &bypass); in sun4i_pwm_apply()
256 dev_err(chip->dev, "period exceeds the maximum value\n"); in sun4i_pwm_apply()
258 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
262 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
265 if (sun4i_pwm->data->has_direct_mod_clk_output) { in sun4i_pwm_apply()
266 if (bypass) { in sun4i_pwm_apply()
267 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
270 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
274 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
277 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
279 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
282 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); in sun4i_pwm_apply()
283 ctrl |= BIT_CH(prescaler, pwm->hwpwm); in sun4i_pwm_apply()
287 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_apply()
289 if (state->polarity != PWM_POLARITY_NORMAL) in sun4i_pwm_apply()
290 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
292 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
294 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
296 if (state->enabled) in sun4i_pwm_apply()
297 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
301 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
303 if (state->enabled) in sun4i_pwm_apply()
313 spin_lock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
315 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
316 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
318 spin_unlock(&sun4i_pwm->ctrl_lock); in sun4i_pwm_apply()
320 clk_disable_unprepare(sun4i_pwm->clk); in sun4i_pwm_apply()
360 .compatible = "allwinner,sun4i-a10-pwm",
363 .compatible = "allwinner,sun5i-a10s-pwm",
366 .compatible = "allwinner,sun5i-a13-pwm",
369 .compatible = "allwinner,sun7i-a20-pwm",
372 .compatible = "allwinner,sun8i-h3-pwm",
375 .compatible = "allwinner,sun50i-a64-pwm",
378 .compatible = "allwinner,sun50i-h6-pwm",
391 sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL); in sun4i_pwm_probe()
393 return -ENOMEM; in sun4i_pwm_probe()
395 sun4ichip->data = of_device_get_match_data(&pdev->dev); in sun4i_pwm_probe()
396 if (!sun4ichip->data) in sun4i_pwm_probe()
397 return -ENODEV; in sun4i_pwm_probe()
399 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_pwm_probe()
400 if (IS_ERR(sun4ichip->base)) in sun4i_pwm_probe()
401 return PTR_ERR(sun4ichip->base); in sun4i_pwm_probe()
414 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod"); in sun4i_pwm_probe()
415 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
416 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
419 if (!sun4ichip->clk) { in sun4i_pwm_probe()
420 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL); in sun4i_pwm_probe()
421 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
422 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
426 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); in sun4i_pwm_probe()
427 if (IS_ERR(sun4ichip->bus_clk)) in sun4i_pwm_probe()
428 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk), in sun4i_pwm_probe()
431 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in sun4i_pwm_probe()
432 if (IS_ERR(sun4ichip->rst)) in sun4i_pwm_probe()
433 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst), in sun4i_pwm_probe()
437 ret = reset_control_deassert(sun4ichip->rst); in sun4i_pwm_probe()
439 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", in sun4i_pwm_probe()
448 ret = clk_prepare_enable(sun4ichip->bus_clk); in sun4i_pwm_probe()
450 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", in sun4i_pwm_probe()
455 sun4ichip->chip.dev = &pdev->dev; in sun4i_pwm_probe()
456 sun4ichip->chip.ops = &sun4i_pwm_ops; in sun4i_pwm_probe()
457 sun4ichip->chip.npwm = sun4ichip->data->npwm; in sun4i_pwm_probe()
459 spin_lock_init(&sun4ichip->ctrl_lock); in sun4i_pwm_probe()
461 ret = pwmchip_add(&sun4ichip->chip); in sun4i_pwm_probe()
463 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); in sun4i_pwm_probe()
472 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_probe()
474 reset_control_assert(sun4ichip->rst); in sun4i_pwm_probe()
483 pwmchip_remove(&sun4ichip->chip); in sun4i_pwm_remove()
485 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_remove()
486 reset_control_assert(sun4ichip->rst); in sun4i_pwm_remove()
491 .name = "sun4i-pwm",
499 MODULE_ALIAS("platform:sun4i-pwm");
500 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");