1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/pwm.h>
28  * struct crystalcove_pwm - Crystal Cove PWM controller
47 	/* clk_div 1 - 128, maps to register values 0-127 */  in crc_pwm_calc_clk_div()
49 		clk_div--;  in crc_pwm_calc_clk_div()
54 static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in crc_pwm_apply()  argument
58 	struct device *dev = crc_pwm->chip.dev;  in crc_pwm_apply()
61 	if (state->period > PWM_MAX_PERIOD_NS) {  in crc_pwm_apply()
62 		dev_err(dev, "un-supported period_ns\n");  in crc_pwm_apply()
63 		return -EINVAL;  in crc_pwm_apply()
66 	if (state->polarity != PWM_POLARITY_NORMAL)  in crc_pwm_apply()
67 		return -EINVAL;  in crc_pwm_apply()
69 	if (pwm_is_enabled(pwm) && !state->enabled) {  in crc_pwm_apply()
70 		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);  in crc_pwm_apply()
77 	if (pwm_get_duty_cycle(pwm) != state->duty_cycle ||  in crc_pwm_apply()
78 	    pwm_get_period(pwm) != state->period) {  in crc_pwm_apply()
79 		u64 level = state->duty_cycle * PWM_MAX_LEVEL;  in crc_pwm_apply()
81 		do_div(level, state->period);  in crc_pwm_apply()
83 		err = regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);  in crc_pwm_apply()
90 	if (pwm_is_enabled(pwm) && state->enabled &&  in crc_pwm_apply()
91 	    pwm_get_period(pwm) != state->period) {  in crc_pwm_apply()
93 		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);  in crc_pwm_apply()
100 	if (pwm_get_period(pwm) != state->period ||  in crc_pwm_apply()
101 	    pwm_is_enabled(pwm) != state->enabled) {  in crc_pwm_apply()
102 		int clk_div = crc_pwm_calc_clk_div(state->period);  in crc_pwm_apply()
103 		int pwm_output_enable = state->enabled ? PWM_OUTPUT_ENABLE : 0;  in crc_pwm_apply()
105 		err = regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,  in crc_pwm_apply()
113 	if (!pwm_is_enabled(pwm) && state->enabled) {  in crc_pwm_apply()
114 		err = regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);  in crc_pwm_apply()
124 static int crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in crc_pwm_get_state()  argument
128 	struct device *dev = crc_pwm->chip.dev;  in crc_pwm_get_state()
132 	error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg);  in crc_pwm_get_state()
138 	error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg);  in crc_pwm_get_state()
146 	state->period =  in crc_pwm_get_state()
148 	state->duty_cycle =  in crc_pwm_get_state()
149 		DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL);  in crc_pwm_get_state()
150 	state->polarity = PWM_POLARITY_NORMAL;  in crc_pwm_get_state()
151 	state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE);  in crc_pwm_get_state()
163 	struct crystalcove_pwm *pwm;  in crystalcove_pwm_probe()  local
164 	struct device *dev = pdev->dev.parent;  in crystalcove_pwm_probe()
167 	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);  in crystalcove_pwm_probe()
168 	if (!pwm)  in crystalcove_pwm_probe()
169 		return -ENOMEM;  in crystalcove_pwm_probe()
171 	pwm->chip.dev = &pdev->dev;  in crystalcove_pwm_probe()
172 	pwm->chip.ops = &crc_pwm_ops;  in crystalcove_pwm_probe()
173 	pwm->chip.npwm = 1;  in crystalcove_pwm_probe()
176 	pwm->regmap = pmic->regmap;  in crystalcove_pwm_probe()
178 	return devm_pwmchip_add(&pdev->dev, &pwm->chip);  in crystalcove_pwm_probe()