Lines Matching refs:bank
157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
180 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_speed() argument
183 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
184 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
187 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_bias() argument
190 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
191 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
196 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, in __stm32_gpio_set() argument
199 stm32_gpio_backup_value(bank, offset, value); in __stm32_gpio_set()
204 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
209 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_request() local
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request()
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
230 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get() local
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get()
237 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_set() local
239 __stm32_gpio_set(bank, offset, value); in stm32_gpio_set()
250 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_direction_output() local
252 __stm32_gpio_set(bank, offset, value); in stm32_gpio_direction_output()
261 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_to_irq() local
264 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
274 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_get_direction() local
279 stm32_pmx_get_mode(bank, pin, &mode, &alt); in stm32_gpio_get_direction()
294 struct stm32_gpio_bank *bank = gpiochip_get_data(chip); in stm32_gpio_init_valid_mask() local
295 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_init_valid_mask()
302 if (bank->secure_control) { in stm32_gpio_init_valid_mask()
304 sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR); in stm32_gpio_init_valid_mask()
309 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i); in stm32_gpio_init_valid_mask()
332 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger() local
336 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
340 level = stm32_gpio_get(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
341 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
342 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
354 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type() local
373 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
380 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources() local
381 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources()
384 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
388 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
400 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources() local
402 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
440 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate() local
441 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate()
453 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
465 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc() local
468 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_alloc()
496 bank); in stm32_gpio_domain_alloc()
504 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_free() local
505 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_free()
768 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank, in stm32_pmx_set_mode() argument
771 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode()
778 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
789 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
792 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
794 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
797 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
802 stm32_gpio_backup_mode(bank, pin, mode, alt); in stm32_pmx_set_mode()
805 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
810 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, in stm32_pmx_get_mode() argument
818 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
820 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
824 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
828 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
839 struct stm32_gpio_bank *bank; in stm32_pmx_set_mux() local
853 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
859 return stm32_pmx_set_mode(bank, pin, mode, alt); in stm32_pmx_set_mux()
866 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction() local
869 return stm32_pmx_set_mode(bank, pin, !input, 0); in stm32_pmx_gpio_set_direction()
903 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank, in stm32_pconf_set_driving() argument
906 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving()
911 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
922 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
925 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
930 stm32_gpio_backup_driving(bank, offset, drive); in stm32_pconf_set_driving()
933 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
938 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, in stm32_pconf_get_driving() argument
944 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
946 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
949 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
954 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank, in stm32_pconf_set_speed() argument
957 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed()
962 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
973 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
976 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
981 stm32_gpio_backup_speed(bank, offset, speed); in stm32_pconf_set_speed()
984 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
989 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, in stm32_pconf_get_speed() argument
995 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
997 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
1000 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
1005 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank, in stm32_pconf_set_bias() argument
1008 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias()
1013 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1024 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1027 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1032 stm32_gpio_backup_bias(bank, offset, bias); in stm32_pconf_set_bias()
1035 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1040 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, in stm32_pconf_get_bias() argument
1046 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1048 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1051 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1056 static bool stm32_pconf_get(struct stm32_gpio_bank *bank, in stm32_pconf_get() argument
1062 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1065 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1068 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1071 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1082 struct stm32_gpio_bank *bank; in stm32_pconf_parse_conf() local
1091 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1101 ret = stm32_pconf_set_driving(bank, offset, 0); in stm32_pconf_parse_conf()
1104 ret = stm32_pconf_set_driving(bank, offset, 1); in stm32_pconf_parse_conf()
1107 ret = stm32_pconf_set_speed(bank, offset, arg); in stm32_pconf_parse_conf()
1110 ret = stm32_pconf_set_bias(bank, offset, 0); in stm32_pconf_parse_conf()
1113 ret = stm32_pconf_set_bias(bank, offset, 1); in stm32_pconf_parse_conf()
1116 ret = stm32_pconf_set_bias(bank, offset, 2); in stm32_pconf_parse_conf()
1119 __stm32_gpio_set(bank, offset, arg); in stm32_pconf_parse_conf()
1200 struct stm32_gpio_bank *bank; in stm32_pconf_dbg_show() local
1215 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1223 stm32_pmx_get_mode(bank, offset, &mode, &alt); in stm32_pconf_dbg_show()
1224 bias = stm32_pconf_get_bias(bank, offset); in stm32_pconf_dbg_show()
1231 val = stm32_pconf_get(bank, offset, true); in stm32_pconf_dbg_show()
1239 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1240 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1241 val = stm32_pconf_get(bank, offset, false); in stm32_pconf_dbg_show()
1251 drive = stm32_pconf_get_driving(bank, offset); in stm32_pconf_dbg_show()
1252 speed = stm32_pconf_get_speed(bank, offset); in stm32_pconf_dbg_show()
1278 struct stm32_gpio_bank *bank, in stm32_pctrl_get_desc_pin_from_gpio() argument
1281 unsigned int stm32_pin_nb = bank->bank_nr * STM32_GPIO_PINS_PER_BANK + offset; in stm32_pctrl_get_desc_pin_from_gpio()
1303 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank() local
1305 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1314 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1315 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1320 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1321 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1322 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1324 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1326 fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1330 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1338 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1339 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1344 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1352 bank->gpio_chip.base = -1; in stm32_gpiolib_register_bank()
1354 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1355 bank->gpio_chip.fwnode = fwnode; in stm32_gpiolib_register_bank()
1356 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1357 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1358 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1359 bank->secure_control = pctl->match_data->secure_control; in stm32_gpiolib_register_bank()
1360 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1364 bank->fwnode = fwnode; in stm32_gpiolib_register_bank()
1366 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1367 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1368 bank); in stm32_gpiolib_register_bank()
1370 if (!bank->domain) in stm32_gpiolib_register_bank()
1379 stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i); in stm32_gpiolib_register_bank()
1389 bank->gpio_chip.names = (const char * const *)names; in stm32_gpiolib_register_bank()
1391 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1397 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1628 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe() local
1631 bank->rstc = of_reset_control_get_exclusive(np, NULL); in stm32_pctl_probe()
1632 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) { in stm32_pctl_probe()
1668 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe() local
1670 gpiochip_remove(&bank->gpio_chip); in stm32_pctl_probe()
1683 struct stm32_gpio_bank *bank; in stm32_pinctrl_restore_gpio_regs() local
1699 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1701 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1703 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1706 ret = stm32_pmx_set_mode(bank, offset, mode, alt); in stm32_pinctrl_restore_gpio_regs()
1711 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1713 __stm32_gpio_set(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1716 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1718 ret = stm32_pconf_set_driving(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1722 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1724 ret = stm32_pconf_set_speed(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1728 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1730 ret = stm32_pconf_set_bias(bank, offset, val); in stm32_pinctrl_restore_gpio_regs()
1735 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()