506 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)  in qusb2_phy_override_phy_params()  argument
508 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_override_phy_params()
509 	struct override_params *or = &qphy->overrides;  in qusb2_phy_override_phy_params()
512 		qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,  in qusb2_phy_override_phy_params()
517 		qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,  in qusb2_phy_override_phy_params()
522 		qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,  in qusb2_phy_override_phy_params()
527 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
532 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_override_phy_params()
539 			qusb2_setbits(qphy->base,  in qusb2_phy_override_phy_params()
543 			qusb2_clrbits(qphy->base,  in qusb2_phy_override_phy_params()
549 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],  in qusb2_phy_override_phy_params()
559 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)  in qusb2_phy_set_tune2_param()  argument
561 	struct device *dev = &qphy->phy->dev;  in qusb2_phy_set_tune2_param()
562 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_set_tune2_param()
566 	if (!qphy->cell)  in qusb2_phy_set_tune2_param()
576 	val = nvmem_cell_read(qphy->cell, NULL);  in qusb2_phy_set_tune2_param()
590 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],  in qusb2_phy_set_tune2_param()
593 		qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],  in qusb2_phy_set_tune2_param()
600 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_set_mode()  local
602 	qphy->mode = mode;  in qusb2_phy_set_mode()
609 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_suspend()  local
610 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_suspend()
613 	dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_suspend()
615 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_suspend()
627 	switch (qphy->mode) {  in qusb2_phy_runtime_suspend()
645 	writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_suspend()
649 		qusb2_setbits(qphy->base,  in qusb2_phy_runtime_suspend()
656 	if (qphy->mode != PHY_MODE_INVALID) {  in qusb2_phy_runtime_suspend()
657 		qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
660 		qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],  in qusb2_phy_runtime_suspend()
664 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_runtime_suspend()
665 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_runtime_suspend()
667 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_suspend()
668 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_suspend()
675 	struct qusb2_phy *qphy = dev_get_drvdata(dev);  in qusb2_phy_runtime_resume()  local
676 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_runtime_resume()
679 	dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);  in qusb2_phy_runtime_resume()
681 	if (!qphy->phy_initialized) {  in qusb2_phy_runtime_resume()
686 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_runtime_resume()
692 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
698 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_runtime_resume()
699 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_runtime_resume()
706 	writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);  in qusb2_phy_runtime_resume()
710 		qusb2_clrbits(qphy->base,  in qusb2_phy_runtime_resume()
718 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_runtime_resume()
720 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_runtime_resume()
727 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_init()  local
728 	const struct qusb2_phy_cfg *cfg = qphy->cfg;  in qusb2_phy_init()
736 	ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
740 	ret = clk_prepare_enable(qphy->iface_clk);  in qusb2_phy_init()
747 	ret = clk_prepare_enable(qphy->cfg_ahb_clk);  in qusb2_phy_init()
754 	ret = reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
763 	ret = reset_control_deassert(qphy->phy_reset);  in qusb2_phy_init()
770 	qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
771 		      qphy->cfg->disable_ctrl);  in qusb2_phy_init()
775 		val = readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
778 	qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,  in qusb2_phy_init()
782 	qusb2_phy_override_phy_params(qphy);  in qusb2_phy_init()
785 	qusb2_phy_set_tune2_param(qphy);  in qusb2_phy_init()
788 	qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_init()
799 	qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;  in qusb2_phy_init()
807 	if (qphy->tcsr) {  in qusb2_phy_init()
808 		ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,  in qusb2_phy_init()
819 			qphy->has_se_clk_scheme = false;  in qusb2_phy_init()
826 	if (!qphy->has_se_clk_scheme) {  in qusb2_phy_init()
827 		ret = clk_prepare_enable(qphy->ref_clk);  in qusb2_phy_init()
836 		if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
841 		writel(val, qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
844 		readl(qphy->base + QUSB2PHY_PLL_TEST);  in qusb2_phy_init()
850 	val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);  in qusb2_phy_init()
857 	qphy->phy_initialized = true;  in qusb2_phy_init()
862 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_init()
863 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_init()
865 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_init()
867 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_init()
869 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_init()
871 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_init()
878 	struct qusb2_phy *qphy = phy_get_drvdata(phy);  in qusb2_phy_exit()  local
881 	qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],  in qusb2_phy_exit()
882 		      qphy->cfg->disable_ctrl);  in qusb2_phy_exit()
884 	if (!qphy->has_se_clk_scheme)  in qusb2_phy_exit()
885 		clk_disable_unprepare(qphy->ref_clk);  in qusb2_phy_exit()
887 	reset_control_assert(qphy->phy_reset);  in qusb2_phy_exit()
889 	clk_disable_unprepare(qphy->cfg_ahb_clk);  in qusb2_phy_exit()
890 	clk_disable_unprepare(qphy->iface_clk);  in qusb2_phy_exit()
892 	regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);  in qusb2_phy_exit()
894 	qphy->phy_initialized = false;  in qusb2_phy_exit()
960 	struct qusb2_phy *qphy;  in qusb2_phy_probe()  local
968 	qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);  in qusb2_phy_probe()
969 	if (!qphy)  in qusb2_phy_probe()
971 	or = &qphy->overrides;  in qusb2_phy_probe()
973 	qphy->base = devm_platform_ioremap_resource(pdev, 0);  in qusb2_phy_probe()
974 	if (IS_ERR(qphy->base))  in qusb2_phy_probe()
975 		return PTR_ERR(qphy->base);  in qusb2_phy_probe()
977 	qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");  in qusb2_phy_probe()
978 	if (IS_ERR(qphy->cfg_ahb_clk))  in qusb2_phy_probe()
979 		return dev_err_probe(dev, PTR_ERR(qphy->cfg_ahb_clk),  in qusb2_phy_probe()
982 	qphy->ref_clk = devm_clk_get(dev, "ref");  in qusb2_phy_probe()
983 	if (IS_ERR(qphy->ref_clk))  in qusb2_phy_probe()
984 		return dev_err_probe(dev, PTR_ERR(qphy->ref_clk),  in qusb2_phy_probe()
987 	qphy->iface_clk = devm_clk_get_optional(dev, "iface");  in qusb2_phy_probe()
988 	if (IS_ERR(qphy->iface_clk))  in qusb2_phy_probe()
989 		return PTR_ERR(qphy->iface_clk);  in qusb2_phy_probe()
991 	qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);  in qusb2_phy_probe()
992 	if (IS_ERR(qphy->phy_reset)) {  in qusb2_phy_probe()
994 		return PTR_ERR(qphy->phy_reset);  in qusb2_phy_probe()
997 	num = ARRAY_SIZE(qphy->vregs);  in qusb2_phy_probe()
999 		qphy->vregs[i].supply = qusb2_phy_vreg_names[i];  in qusb2_phy_probe()
1001 	ret = devm_regulator_bulk_get(dev, num, qphy->vregs);  in qusb2_phy_probe()
1007 	qphy->cfg = of_device_get_match_data(dev);  in qusb2_phy_probe()
1009 	qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,  in qusb2_phy_probe()
1011 	if (IS_ERR(qphy->tcsr)) {  in qusb2_phy_probe()
1013 		qphy->tcsr = NULL;  in qusb2_phy_probe()
1016 	qphy->cell = devm_nvmem_cell_get(dev, NULL);  in qusb2_phy_probe()
1017 	if (IS_ERR(qphy->cell)) {  in qusb2_phy_probe()
1018 		if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)  in qusb2_phy_probe()
1020 		qphy->cell = NULL;  in qusb2_phy_probe()
1081 	qphy->phy = generic_phy;  in qusb2_phy_probe()
1083 	dev_set_drvdata(dev, qphy);  in qusb2_phy_probe()
1084 	phy_set_drvdata(generic_phy, qphy);  in qusb2_phy_probe()