Lines Matching refs:dev

84 int pcie_failed_link_retrain(struct pci_dev *dev)  in pcie_failed_link_retrain()  argument
93 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || in pcie_failed_link_retrain()
94 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
97 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); in pcie_failed_link_retrain()
98 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); in pcie_failed_link_retrain()
103 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
107 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); in pcie_failed_link_retrain()
109 ret = pcie_retrain_link(dev, false); in pcie_failed_link_retrain()
111 pci_info(dev, "retraining failed\n"); in pcie_failed_link_retrain()
112 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, in pcie_failed_link_retrain()
114 pcie_retrain_link(dev, true); in pcie_failed_link_retrain()
118 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); in pcie_failed_link_retrain()
123 pci_match_id(ids, dev)) { in pcie_failed_link_retrain()
126 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); in pcie_failed_link_retrain()
127 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); in pcie_failed_link_retrain()
130 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2); in pcie_failed_link_retrain()
132 ret = pcie_retrain_link(dev, false); in pcie_failed_link_retrain()
134 pci_info(dev, "retraining failed\n"); in pcie_failed_link_retrain()
142 static ktime_t fixup_debug_start(struct pci_dev *dev, in fixup_debug_start() argument
143 void (*fn)(struct pci_dev *dev)) in fixup_debug_start() argument
146 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); in fixup_debug_start()
151 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, in fixup_debug_report() argument
152 void (*fn)(struct pci_dev *dev)) in fixup_debug_report() argument
161 pci_info(dev, "%pS took %lld usecs\n", fn, duration); in fixup_debug_report()
164 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, in pci_do_fixups() argument
170 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
172 (f->vendor == dev->vendor || in pci_do_fixups()
174 (f->device == dev->device || in pci_do_fixups()
176 void (*hook)(struct pci_dev *dev); in pci_do_fixups()
182 calltime = fixup_debug_start(dev, hook); in pci_do_fixups()
183 hook(dev); in pci_do_fixups()
184 fixup_debug_report(dev, calltime, hook); in pci_do_fixups()
207 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) in pci_fixup_device() argument
258 pci_do_fixups(dev, start, end); in pci_fixup_device()
264 struct pci_dev *dev = NULL; in pci_apply_final_quirks() local
272 for_each_pci_dev(dev) { in pci_apply_final_quirks()
273 pci_fixup_device(pci_fixup_final, dev); in pci_apply_final_quirks()
280 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); in pci_apply_final_quirks()
286 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", in pci_apply_final_quirks()
309 static void quirk_mmio_always_on(struct pci_dev *dev) in quirk_mmio_always_on() argument
311 dev->mmio_always_on = 1; in quirk_mmio_always_on()
327 static void quirk_passive_release(struct pci_dev *dev) in quirk_passive_release() argument
357 static void quirk_isa_dma_hangs(struct pci_dev *dev) in quirk_isa_dma_hangs() argument
361 pci_info(dev, "Activating ISA DMA hang workarounds\n"); in quirk_isa_dma_hangs()
382 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) in quirk_tigerpoint_bm_sts() argument
387 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
392 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); in quirk_tigerpoint_bm_sts()
400 static void quirk_nopcipci(struct pci_dev *dev) in quirk_nopcipci() argument
403 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
410 static void quirk_nopciamd(struct pci_dev *dev) in quirk_nopciamd() argument
413 pci_read_config_byte(dev, 0x08, &rev); in quirk_nopciamd()
416 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
423 static void quirk_triton(struct pci_dev *dev) in quirk_triton() argument
426 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
445 static void quirk_vialatency(struct pci_dev *dev) in quirk_vialatency() argument
486 pci_read_config_byte(dev, 0x76, &busarb); in quirk_vialatency()
494 pci_write_config_byte(dev, 0x76, busarb); in quirk_vialatency()
495 pci_info(dev, "Applying VIA southbridge workaround\n"); in quirk_vialatency()
508 static void quirk_viaetbf(struct pci_dev *dev) in quirk_viaetbf() argument
511 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
517 static void quirk_vsfx(struct pci_dev *dev) in quirk_vsfx() argument
520 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
531 static void quirk_alimagik(struct pci_dev *dev) in quirk_alimagik() argument
534 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
542 static void quirk_natoma(struct pci_dev *dev) in quirk_natoma() argument
545 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
560 static void quirk_citrine(struct pci_dev *dev) in quirk_citrine() argument
562 dev->cfg_size = 0xA0; in quirk_citrine()
570 static void quirk_nfp6000(struct pci_dev *dev) in quirk_nfp6000() argument
572 dev->cfg_size = 0x600; in quirk_nfp6000()
580 static void quirk_extend_bar_to_page(struct pci_dev *dev) in quirk_extend_bar_to_page() argument
585 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
591 pci_info(dev, "expanded BAR %d to page size: %pR\n", in quirk_extend_bar_to_page()
602 static void quirk_s3_64M(struct pci_dev *dev) in quirk_s3_64M() argument
604 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
615 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, in quirk_io() argument
620 struct resource *res = dev->resource + pos; in quirk_io()
622 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region); in quirk_io()
627 res->name = pci_name(dev); in quirk_io()
636 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
638 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n", in quirk_io()
651 static void quirk_cs5536_vsa(struct pci_dev *dev) in quirk_cs5536_vsa() argument
655 if (pci_resource_len(dev, 0) != 8) { in quirk_cs5536_vsa()
656 quirk_io(dev, 0, 8, name); /* SMB */ in quirk_cs5536_vsa()
657 quirk_io(dev, 1, 256, name); /* GPIO */ in quirk_cs5536_vsa()
658 quirk_io(dev, 2, 64, name); /* MFGPT */ in quirk_cs5536_vsa()
659 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", in quirk_cs5536_vsa()
665 static void quirk_io_region(struct pci_dev *dev, int port, in quirk_io_region() argument
670 struct resource *res = dev->resource + nr; in quirk_io_region()
672 pci_read_config_word(dev, port, &region); in quirk_io_region()
678 res->name = pci_name(dev); in quirk_io_region()
684 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
686 if (!pci_claim_resource(dev, nr)) in quirk_io_region()
687 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); in quirk_io_region()
694 static void quirk_ati_exploding_mce(struct pci_dev *dev) in quirk_ati_exploding_mce() argument
696 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); in quirk_ati_exploding_mce()
766 static void quirk_ali7101_acpi(struct pci_dev *dev) in quirk_ali7101_acpi() argument
768 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); in quirk_ali7101_acpi()
769 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); in quirk_ali7101_acpi()
773 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int e… in piix4_io_quirk() argument
778 pci_read_config_dword(dev, port, &devres); in piix4_io_quirk()
796 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
799 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int … in piix4_mem_quirk() argument
804 pci_read_config_dword(dev, port, &devres); in piix4_mem_quirk()
822 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
831 static void quirk_piix4_acpi(struct pci_dev *dev) in quirk_piix4_acpi() argument
835 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); in quirk_piix4_acpi()
836 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); in quirk_piix4_acpi()
839 pci_read_config_dword(dev, 0x5c, &res_a); in quirk_piix4_acpi()
841 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); in quirk_piix4_acpi()
842 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); in quirk_piix4_acpi()
848 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); in quirk_piix4_acpi()
849 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); in quirk_piix4_acpi()
853 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); in quirk_piix4_acpi()
854 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); in quirk_piix4_acpi()
856 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); in quirk_piix4_acpi()
857 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); in quirk_piix4_acpi()
878 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) in quirk_ich4_lpc_acpi() argument
889 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in quirk_ich4_lpc_acpi()
891 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in quirk_ich4_lpc_acpi()
894 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); in quirk_ich4_lpc_acpi()
896 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in quirk_ich4_lpc_acpi()
910 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) in ich6_lpc_acpi_gpio() argument
914 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); in ich6_lpc_acpi_gpio()
916 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, in ich6_lpc_acpi_gpio()
919 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); in ich6_lpc_acpi_gpio()
921 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, in ich6_lpc_acpi_gpio()
925 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, in ich6_lpc_generic_decode() argument
931 pci_read_config_dword(dev, reg, &val); in ich6_lpc_generic_decode()
954 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
957 static void quirk_ich6_lpc(struct pci_dev *dev) in quirk_ich6_lpc() argument
960 ich6_lpc_acpi_gpio(dev); in quirk_ich6_lpc()
963 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
964 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
969 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, in ich7_lpc_generic_decode() argument
975 pci_read_config_dword(dev, reg, &val); in ich7_lpc_generic_decode()
990 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); in ich7_lpc_generic_decode()
994 static void quirk_ich7_lpc(struct pci_dev *dev) in quirk_ich7_lpc() argument
997 ich6_lpc_acpi_gpio(dev); in quirk_ich7_lpc()
1000 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
1001 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
1002 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
1003 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
1023 static void quirk_vt82c586_acpi(struct pci_dev *dev) in quirk_vt82c586_acpi() argument
1025 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
1026 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, in quirk_vt82c586_acpi()
1037 static void quirk_vt82c686_acpi(struct pci_dev *dev) in quirk_vt82c686_acpi() argument
1039 quirk_vt82c586_acpi(dev); in quirk_vt82c686_acpi()
1041 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, in quirk_vt82c686_acpi()
1044 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); in quirk_vt82c686_acpi()
1053 static void quirk_vt8235_acpi(struct pci_dev *dev) in quirk_vt8235_acpi() argument
1055 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); in quirk_vt8235_acpi()
1056 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); in quirk_vt8235_acpi()
1064 static void quirk_xio2000a(struct pci_dev *dev) in quirk_xio2000a() argument
1069 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1070 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1090 static void quirk_via_ioapic(struct pci_dev *dev) in quirk_via_ioapic() argument
1099 pci_info(dev, "%s VIA external APIC routing\n", in quirk_via_ioapic()
1103 pci_write_config_byte(dev, 0x58, tmp); in quirk_via_ioapic()
1114 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) in quirk_via_vt8237_bypass_apic_deassert() argument
1119 pci_read_config_byte(dev, 0x5B, &misc_control2); in quirk_via_vt8237_bypass_apic_deassert()
1121 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1122 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); in quirk_via_vt8237_bypass_apic_deassert()
1137 static void quirk_amd_ioapic(struct pci_dev *dev) in quirk_amd_ioapic() argument
1139 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1140 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); in quirk_amd_ioapic()
1141 pci_warn(dev, " : booting with the \"noapic\" option\n"); in quirk_amd_ioapic()
1149 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) in quirk_cavium_sriov_rnm_link() argument
1152 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1153 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1162 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) in quirk_amd_8131_mmrbc() argument
1164 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1165 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1166 dev->revision); in quirk_amd_8131_mmrbc()
1167 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1195 static void quirk_via_bridge(struct pci_dev *dev) in quirk_via_bridge() argument
1198 switch (dev->device) { in quirk_via_bridge()
1205 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1206 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1243 static void quirk_via_vlink(struct pci_dev *dev) in quirk_via_vlink() argument
1251 new_irq = dev->irq; in quirk_via_vlink()
1258 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1259 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1266 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in quirk_via_vlink()
1268 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", in quirk_via_vlink()
1271 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); in quirk_via_vlink()
1281 static void quirk_vt82c598_id(struct pci_dev *dev) in quirk_vt82c598_id() argument
1283 pci_write_config_byte(dev, 0xfc, 0); in quirk_vt82c598_id()
1284 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1294 static void quirk_cardbus_legacy(struct pci_dev *dev) in quirk_cardbus_legacy() argument
1296 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); in quirk_cardbus_legacy()
1310 static void quirk_amd_ordering(struct pci_dev *dev) in quirk_amd_ordering() argument
1313 pci_read_config_dword(dev, 0x4C, &pcic); in quirk_amd_ordering()
1316 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
1317 pci_write_config_dword(dev, 0x4C, pcic); in quirk_amd_ordering()
1318 pci_read_config_dword(dev, 0x84, &pcic); in quirk_amd_ordering()
1320 pci_write_config_dword(dev, 0x84, pcic); in quirk_amd_ordering()
1333 static void quirk_dunord(struct pci_dev *dev) in quirk_dunord() argument
1335 struct resource *r = &dev->resource[1]; in quirk_dunord()
1348 static void quirk_transparent_bridge(struct pci_dev *dev) in quirk_transparent_bridge() argument
1350 dev->transparent = 1; in quirk_transparent_bridge()
1361 static void quirk_mediagx_master(struct pci_dev *dev) in quirk_mediagx_master() argument
1365 pci_read_config_byte(dev, 0x41, &reg); in quirk_mediagx_master()
1368 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", in quirk_mediagx_master()
1370 pci_write_config_byte(dev, 0x41, reg); in quirk_mediagx_master()
1475 static void quirk_eisa_bridge(struct pci_dev *dev) in quirk_eisa_bridge() argument
1477 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1508 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) in asus_hides_smbus_hostbridge() argument
1510 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1511 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1512 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1519 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1520 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1526 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1527 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1531 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1532 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1536 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1537 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1541 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1542 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1548 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1549 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1554 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1555 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1560 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1565 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1566 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1567 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1572 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1573 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1579 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1580 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1584 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1585 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1586 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1590 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1591 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1592 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1596 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1597 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1604 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1605 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1616 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1617 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1641 static void asus_hides_smbus_lpc(struct pci_dev *dev) in asus_hides_smbus_lpc() argument
1648 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1650 pci_write_config_word(dev, 0xF2, val & (~0x8)); in asus_hides_smbus_lpc()
1651 pci_read_config_word(dev, 0xF2, &val); in asus_hides_smbus_lpc()
1653 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", in asus_hides_smbus_lpc()
1656 pci_info(dev, "Enabled i801 SMBus device\n"); in asus_hides_smbus_lpc()
1676 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_suspend() argument
1684 pci_read_config_dword(dev, 0xF0, &rcba); in asus_hides_smbus_lpc_ich6_suspend()
1691 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume_early() argument
1705 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6_resume() argument
1712 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); in asus_hides_smbus_lpc_ich6_resume()
1715 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) in asus_hides_smbus_lpc_ich6() argument
1717 asus_hides_smbus_lpc_ich6_suspend(dev); in asus_hides_smbus_lpc_ich6()
1718 asus_hides_smbus_lpc_ich6_resume_early(dev); in asus_hides_smbus_lpc_ich6()
1719 asus_hides_smbus_lpc_ich6_resume(dev); in asus_hides_smbus_lpc_ich6()
1727 static void quirk_sis_96x_smbus(struct pci_dev *dev) in quirk_sis_96x_smbus() argument
1730 pci_read_config_byte(dev, 0x77, &val); in quirk_sis_96x_smbus()
1732 pci_info(dev, "Enabling SiS 96x SMBus\n"); in quirk_sis_96x_smbus()
1733 pci_write_config_byte(dev, 0x77, val & ~0x10); in quirk_sis_96x_smbus()
1755 static void quirk_sis_503(struct pci_dev *dev) in quirk_sis_503() argument
1760 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg); in quirk_sis_503()
1761 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); in quirk_sis_503()
1762 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); in quirk_sis_503()
1764 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); in quirk_sis_503()
1773 dev->device = devid; in quirk_sis_503()
1774 quirk_sis_96x_smbus(dev); in quirk_sis_503()
1785 static void asus_hides_ac97_lpc(struct pci_dev *dev) in asus_hides_ac97_lpc() argument
1790 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1791 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1798 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1800 pci_write_config_byte(dev, 0x50, val & (~0xc0)); in asus_hides_ac97_lpc()
1801 pci_read_config_byte(dev, 0x50, &val); in asus_hides_ac97_lpc()
1803 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", in asus_hides_ac97_lpc()
1806 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); in asus_hides_ac97_lpc()
1892 static void quirk_jmicron_async_suspend(struct pci_dev *dev) in quirk_jmicron_async_suspend() argument
1894 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1895 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1896 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1930 static void quirk_no_msi(struct pci_dev *dev) in quirk_no_msi() argument
1932 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); in quirk_no_msi()
1933 dev->no_msi = 1; in quirk_no_msi()
1980 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1981 device_create_managed_software_node(&pdev->dev, properties, NULL)) in quirk_huawei_pcie_sva()
1995 static void quirk_pcie_pxh(struct pci_dev *dev) in quirk_pcie_pxh() argument
1997 dev->no_msi = 1; in quirk_pcie_pxh()
1998 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); in quirk_pcie_pxh()
2010 static void quirk_intel_pcie_pm(struct pci_dev *dev) in quirk_intel_pcie_pm() argument
2013 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
2037 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) in quirk_d3hot_delay() argument
2039 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
2042 dev->d3hot_delay = delay; in quirk_d3hot_delay()
2043 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
2044 dev->d3hot_delay); in quirk_d3hot_delay()
2047 static void quirk_radeon_pm(struct pci_dev *dev) in quirk_radeon_pm() argument
2049 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
2050 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
2051 quirk_d3hot_delay(dev, 20); in quirk_radeon_pm()
2060 static void quirk_nvidia_hda_pm(struct pci_dev *dev) in quirk_nvidia_hda_pm() argument
2062 quirk_d3hot_delay(dev, 20); in quirk_nvidia_hda_pm()
2077 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) in quirk_ryzen_xhci_d3hot() argument
2079 quirk_d3hot_delay(dev, 20); in quirk_ryzen_xhci_d3hot()
2115 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) in quirk_reroute_to_boot_interrupts_intel() argument
2121 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2122 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", in quirk_reroute_to_boot_interrupts_intel()
2123 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2167 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) in quirk_disable_intel_boot_interrupt() argument
2175 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2177 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, in quirk_disable_intel_boot_interrupt()
2180 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, in quirk_disable_intel_boot_interrupt()
2188 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, in quirk_disable_intel_boot_interrupt()
2191 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, in quirk_disable_intel_boot_interrupt()
2197 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_intel_boot_interrupt()
2198 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2243 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) in quirk_disable_broadcom_boot_interrupt() argument
2251 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
2252 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | in quirk_disable_broadcom_boot_interrupt()
2260 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); in quirk_disable_broadcom_boot_interrupt()
2262 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_broadcom_boot_interrupt()
2263 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2280 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_813x_boot_interrupt() argument
2286 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2287 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2290 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
2292 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); in quirk_disable_amd_813x_boot_interrupt()
2294 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_813x_boot_interrupt()
2295 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2304 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) in quirk_disable_amd_8111_boot_interrupt() argument
2311 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); in quirk_disable_amd_8111_boot_interrupt()
2313 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", in quirk_disable_amd_8111_boot_interrupt()
2314 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2317 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); in quirk_disable_amd_8111_boot_interrupt()
2318 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", in quirk_disable_amd_8111_boot_interrupt()
2319 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2330 static void quirk_tc86c001_ide(struct pci_dev *dev) in quirk_tc86c001_ide() argument
2332 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2351 static void quirk_plx_pci9050(struct pci_dev *dev) in quirk_plx_pci9050() argument
2356 if (dev->revision >= 2) in quirk_plx_pci9050()
2359 if (pci_resource_len(dev, bar) == 0x80 && in quirk_plx_pci9050()
2360 (pci_resource_start(dev, bar) & 0x80)) { in quirk_plx_pci9050()
2361 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2362 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2383 static void quirk_netmos(struct pci_dev *dev) in quirk_netmos() argument
2385 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2386 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2398 switch (dev->device) { in quirk_netmos()
2401 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2402 dev->subsystem_device == 0x0299) in quirk_netmos()
2410 …pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_s… in quirk_netmos()
2411 dev->device, num_parallel, num_serial); in quirk_netmos()
2412 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2413 (dev->class & 0xff); in quirk_netmos()
2420 static void quirk_e100_interrupt(struct pci_dev *dev) in quirk_e100_interrupt() argument
2426 switch (dev->device) { in quirk_e100_interrupt()
2453 pci_read_config_word(dev, PCI_COMMAND, &command); in quirk_e100_interrupt()
2455 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) in quirk_e100_interrupt()
2462 if (dev->pm_cap) { in quirk_e100_interrupt()
2463 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2469 csr = ioremap(pci_resource_start(dev, 0), 8); in quirk_e100_interrupt()
2471 pci_warn(dev, "Can't map e100 registers\n"); in quirk_e100_interrupt()
2477 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); in quirk_e100_interrupt()
2490 static void quirk_disable_aspm_l0s(struct pci_dev *dev) in quirk_disable_aspm_l0s() argument
2492 pci_info(dev, "Disabling L0s\n"); in quirk_disable_aspm_l0s()
2493 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); in quirk_disable_aspm_l0s()
2510 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) in quirk_disable_aspm_l0s_l1() argument
2512 pci_info(dev, "Disabling ASPM L0s/L1\n"); in quirk_disable_aspm_l0s_l1()
2513 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); in quirk_disable_aspm_l0s_l1()
2531 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) in quirk_enable_clear_retrain_link() argument
2533 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2534 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); in quirk_enable_clear_retrain_link()
2540 static void fixup_rev1_53c810(struct pci_dev *dev) in fixup_rev1_53c810() argument
2542 u32 class = dev->class; in fixup_rev1_53c810()
2551 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2552 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2553 class, dev->class); in fixup_rev1_53c810()
2558 static void quirk_p64h2_1k_io(struct pci_dev *dev) in quirk_p64h2_1k_io() argument
2562 pci_read_config_word(dev, 0x40, &en1k); in quirk_p64h2_1k_io()
2565 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); in quirk_p64h2_1k_io()
2566 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2576 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) in quirk_nvidia_ck804_pcie_aer_ext_cap() argument
2580 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { in quirk_nvidia_ck804_pcie_aer_ext_cap()
2582 pci_write_config_byte(dev, 0xf41, b | 0x20); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2583 pci_info(dev, "Linking AER extended capability\n"); in quirk_nvidia_ck804_pcie_aer_ext_cap()
2592 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) in quirk_via_cx700_pci_parking_caching() argument
2618 if (pci_read_config_byte(dev, 0x76, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2621 pci_write_config_byte(dev, 0x76, b ^ 0x40); in quirk_via_cx700_pci_parking_caching()
2623 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2627 if (pci_read_config_byte(dev, 0x72, &b) == 0) { in quirk_via_cx700_pci_parking_caching()
2630 pci_write_config_byte(dev, 0x72, 0x0); in quirk_via_cx700_pci_parking_caching()
2633 pci_write_config_byte(dev, 0x75, 0x1); in quirk_via_cx700_pci_parking_caching()
2636 pci_write_config_byte(dev, 0x77, 0x0); in quirk_via_cx700_pci_parking_caching()
2638 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2644 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) in quirk_brcm_5719_limit_mrrs() argument
2648 pci_read_config_dword(dev, 0xf4, &rev); in quirk_brcm_5719_limit_mrrs()
2652 int readrq = pcie_get_readrq(dev); in quirk_brcm_5719_limit_mrrs()
2654 pcie_set_readrq(dev, 2048); in quirk_brcm_5719_limit_mrrs()
2667 static void quirk_unhide_mch_dev6(struct pci_dev *dev) in quirk_unhide_mch_dev6() argument
2671 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) { in quirk_unhide_mch_dev6()
2672 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); in quirk_unhide_mch_dev6()
2673 pci_write_config_byte(dev, 0xF4, reg | 0x02); in quirk_unhide_mch_dev6()
2689 static void quirk_disable_all_msi(struct pci_dev *dev) in quirk_disable_all_msi() argument
2692 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); in quirk_disable_all_msi()
2705 static void quirk_disable_msi(struct pci_dev *dev) in quirk_disable_msi() argument
2707 if (dev->subordinate) { in quirk_disable_msi()
2708 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); in quirk_disable_msi()
2709 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2740 static int msi_ht_cap_enabled(struct pci_dev *dev) in msi_ht_cap_enabled() argument
2744 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in msi_ht_cap_enabled()
2748 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in msi_ht_cap_enabled()
2750 pci_info(dev, "Found %s HT MSI Mapping\n", in msi_ht_cap_enabled()
2756 pos = pci_find_next_ht_capability(dev, pos, in msi_ht_cap_enabled()
2763 static void quirk_msi_ht_cap(struct pci_dev *dev) in quirk_msi_ht_cap() argument
2765 if (!msi_ht_cap_enabled(dev)) in quirk_msi_ht_cap()
2766 quirk_disable_msi(dev); in quirk_msi_ht_cap()
2775 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) in quirk_nvidia_ck804_msi_ht_cap() argument
2783 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2787 quirk_msi_ht_cap(dev); in quirk_nvidia_ck804_msi_ht_cap()
2794 static void ht_enable_msi_mapping(struct pci_dev *dev) in ht_enable_msi_mapping() argument
2798 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_enable_msi_mapping()
2802 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2804 pci_info(dev, "Enabling HT MSI Mapping\n"); in ht_enable_msi_mapping()
2806 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_enable_msi_mapping()
2809 pos = pci_find_next_ht_capability(dev, pos, in ht_enable_msi_mapping()
2824 static void nvenet_msi_disable(struct pci_dev *dev) in nvenet_msi_disable() argument
2831 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2832 dev->no_msi = 1; in nvenet_msi_disable()
2848 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) in pci_quirk_nvidia_tegra_disable_rp_msi() argument
2850 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2911 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) in nvbridge_check_legacy_irq_routing() argument
2915 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) in nvbridge_check_legacy_irq_routing()
2918 pci_read_config_dword(dev, 0x74, &cfg); in nvbridge_check_legacy_irq_routing()
2923 pci_write_config_dword(dev, 0x74, cfg); in nvbridge_check_legacy_irq_routing()
2933 static int ht_check_msi_mapping(struct pci_dev *dev) in ht_check_msi_mapping() argument
2939 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_check_msi_mapping()
2945 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_check_msi_mapping()
2954 pos = pci_find_next_ht_capability(dev, pos, in ht_check_msi_mapping()
2963 struct pci_dev *dev; in host_bridge_with_leaf() local
2970 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2971 if (!dev) in host_bridge_with_leaf()
2975 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in host_bridge_with_leaf()
2977 pci_dev_put(dev); in host_bridge_with_leaf()
2981 if (ht_check_msi_mapping(dev)) { in host_bridge_with_leaf()
2983 pci_dev_put(dev); in host_bridge_with_leaf()
2986 pci_dev_put(dev); in host_bridge_with_leaf()
2995 static int is_end_of_ht_chain(struct pci_dev *dev) in is_end_of_ht_chain() argument
3001 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); in is_end_of_ht_chain()
3006 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); in is_end_of_ht_chain()
3010 pci_read_config_word(dev, pos + ctrl_off, &ctrl); in is_end_of_ht_chain()
3019 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) in nv_ht_enable_msi_mapping() argument
3026 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
3028 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
3044 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && in nv_ht_enable_msi_mapping()
3052 ht_enable_msi_mapping(dev); in nv_ht_enable_msi_mapping()
3058 static void ht_disable_msi_mapping(struct pci_dev *dev) in ht_disable_msi_mapping() argument
3062 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); in ht_disable_msi_mapping()
3066 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
3068 pci_info(dev, "Disabling HT MSI Mapping\n"); in ht_disable_msi_mapping()
3070 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, in ht_disable_msi_mapping()
3073 pos = pci_find_next_ht_capability(dev, pos, in ht_disable_msi_mapping()
3078 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) in __nv_msi_ht_cap_quirk() argument
3088 found = ht_check_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3098 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
3101 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
3111 ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3113 nv_ht_enable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3123 ht_disable_msi_mapping(dev); in __nv_msi_ht_cap_quirk()
3129 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) in nv_msi_ht_cap_quirk_all() argument
3131 return __nv_msi_ht_cap_quirk(dev, 1); in nv_msi_ht_cap_quirk_all()
3136 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) in nv_msi_ht_cap_quirk_leaf() argument
3138 return __nv_msi_ht_cap_quirk(dev, 0); in nv_msi_ht_cap_quirk_leaf()
3143 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) in quirk_msi_intx_disable_bug() argument
3145 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3148 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) in quirk_msi_intx_disable_ati_bug() argument
3163 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3167 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) in quirk_msi_intx_disable_qca_bug() argument
3170 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3171 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); in quirk_msi_intx_disable_qca_bug()
3172 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3245 static void quirk_al_msi_disable(struct pci_dev *dev) in quirk_al_msi_disable() argument
3247 dev->no_msi = 1; in quirk_al_msi_disable()
3248 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3261 static void quirk_hotplug_bridge(struct pci_dev *dev) in quirk_hotplug_bridge() argument
3263 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3293 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) in ricoh_mmc_fixup_rl5c476() argument
3304 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3307 pci_read_config_byte(dev, 0xB7, &disable); in ricoh_mmc_fixup_rl5c476()
3311 pci_read_config_byte(dev, 0x8E, &write_enable); in ricoh_mmc_fixup_rl5c476()
3312 pci_write_config_byte(dev, 0x8E, 0xAA); in ricoh_mmc_fixup_rl5c476()
3313 pci_read_config_byte(dev, 0x8D, &write_target); in ricoh_mmc_fixup_rl5c476()
3314 pci_write_config_byte(dev, 0x8D, 0xB7); in ricoh_mmc_fixup_rl5c476()
3315 pci_write_config_byte(dev, 0xB7, disable | 0x02); in ricoh_mmc_fixup_rl5c476()
3316 pci_write_config_byte(dev, 0x8E, write_enable); in ricoh_mmc_fixup_rl5c476()
3317 pci_write_config_byte(dev, 0x8D, write_target); in ricoh_mmc_fixup_rl5c476()
3319 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); in ricoh_mmc_fixup_rl5c476()
3320 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_rl5c476()
3325 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) in ricoh_mmc_fixup_r5c832() argument
3335 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3349 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3350 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3351 pci_write_config_byte(dev, 0xf9, 0xfc); in ricoh_mmc_fixup_r5c832()
3352 pci_write_config_byte(dev, 0x150, 0x10); in ricoh_mmc_fixup_r5c832()
3353 pci_write_config_byte(dev, 0xf9, 0x00); in ricoh_mmc_fixup_r5c832()
3354 pci_write_config_byte(dev, 0xfc, 0x01); in ricoh_mmc_fixup_r5c832()
3355 pci_write_config_byte(dev, 0xe1, 0x32); in ricoh_mmc_fixup_r5c832()
3356 pci_write_config_byte(dev, 0xfc, 0x00); in ricoh_mmc_fixup_r5c832()
3358 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); in ricoh_mmc_fixup_r5c832()
3361 pci_read_config_byte(dev, 0xCB, &disable); in ricoh_mmc_fixup_r5c832()
3366 pci_read_config_byte(dev, 0xCA, &write_enable); in ricoh_mmc_fixup_r5c832()
3367 pci_write_config_byte(dev, 0xCA, 0x57); in ricoh_mmc_fixup_r5c832()
3368 pci_write_config_byte(dev, 0xCB, disable | 0x02); in ricoh_mmc_fixup_r5c832()
3369 pci_write_config_byte(dev, 0xCA, write_enable); in ricoh_mmc_fixup_r5c832()
3371 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); in ricoh_mmc_fixup_r5c832()
3372 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); in ricoh_mmc_fixup_r5c832()
3396 static void vtd_mask_spec_errors(struct pci_dev *dev) in vtd_mask_spec_errors() argument
3400 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); in vtd_mask_spec_errors()
3401 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); in vtd_mask_spec_errors()
3407 static void fixup_ti816x_class(struct pci_dev *dev) in fixup_ti816x_class() argument
3409 u32 class = dev->class; in fixup_ti816x_class()
3412 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3413 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3414 class, dev->class); in fixup_ti816x_class()
3423 static void fixup_mpss_256(struct pci_dev *dev) in fixup_mpss_256() argument
3425 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3443 static void quirk_intel_mc_errata(struct pci_dev *dev) in quirk_intel_mc_errata() argument
3457 err = pci_read_config_word(dev, 0x48, &rcc); in quirk_intel_mc_errata()
3459 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); in quirk_intel_mc_errata()
3468 err = pci_write_config_word(dev, 0x48, rcc); in quirk_intel_mc_errata()
3470 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); in quirk_intel_mc_errata()
3509 static void quirk_intel_ntb(struct pci_dev *dev) in quirk_intel_ntb() argument
3514 rc = pci_read_config_byte(dev, 0x00D0, &val); in quirk_intel_ntb()
3518 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3520 rc = pci_read_config_byte(dev, 0x00D1, &val); in quirk_intel_ntb()
3524 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3542 static void disable_igfx_irq(struct pci_dev *dev) in disable_igfx_irq() argument
3544 void __iomem *regs = pci_iomap(dev, 0, 0); in disable_igfx_irq()
3546 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3552 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); in disable_igfx_irq()
3557 pci_iounmap(dev, regs); in disable_igfx_irq()
3571 static void quirk_remove_d3hot_delay(struct pci_dev *dev) in quirk_remove_d3hot_delay() argument
3573 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3607 static void quirk_broken_intx_masking(struct pci_dev *dev) in quirk_broken_intx_masking() argument
3609 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3738 static void quirk_no_bus_reset(struct pci_dev *dev) in quirk_no_bus_reset() argument
3740 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3747 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) in quirk_nvidia_no_bus_reset() argument
3749 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3750 quirk_no_bus_reset(dev); in quirk_nvidia_no_bus_reset()
3786 static void quirk_no_pm_reset(struct pci_dev *dev) in quirk_no_pm_reset() argument
3792 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3793 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3859 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) in quirk_apple_poweroff_thunderbolt() argument
3865 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) in quirk_apple_poweroff_thunderbolt()
3877 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3892 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); in quirk_apple_poweroff_thunderbolt()
3912 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) in reset_intel_82599_sfp_virtfn() argument
3923 pcie_flr(dev); in reset_intel_82599_sfp_virtfn()
3934 static int reset_ivb_igd(struct pci_dev *dev, bool probe) in reset_ivb_igd() argument
3943 mmio_base = pci_iomap(dev, 0, 0); in reset_ivb_igd()
3967 pci_warn(dev, "timeout during reset\n"); in reset_ivb_igd()
3972 pci_iounmap(dev, mmio_base); in reset_ivb_igd()
3977 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) in reset_chelsio_generic_dev() argument
3986 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
4002 pci_read_config_word(dev, PCI_COMMAND, &old_command); in reset_chelsio_generic_dev()
4003 pci_write_config_word(dev, PCI_COMMAND, in reset_chelsio_generic_dev()
4010 pci_save_state(dev); in reset_chelsio_generic_dev()
4019 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
4021 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
4026 pcie_flr(dev); in reset_chelsio_generic_dev()
4033 pci_restore_state(dev); in reset_chelsio_generic_dev()
4034 pci_write_config_word(dev, PCI_COMMAND, old_command); in reset_chelsio_generic_dev()
4055 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) in nvme_disable_and_flr() argument
4061 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
4062 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) in nvme_disable_and_flr()
4068 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); in nvme_disable_and_flr()
4072 pci_read_config_word(dev, PCI_COMMAND, &cmd); in nvme_disable_and_flr()
4073 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); in nvme_disable_and_flr()
4110 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); in nvme_disable_and_flr()
4116 pci_iounmap(dev, bar); in nvme_disable_and_flr()
4118 pcie_flr(dev); in nvme_disable_and_flr()
4130 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) in delay_250ms_after_flr() argument
4133 return pcie_reset_flr(dev, PCI_RESET_PROBE); in delay_250ms_after_flr()
4135 pcie_reset_flr(dev, PCI_RESET_DO_RESET); in delay_250ms_after_flr()
4228 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) in pci_dev_specific_reset() argument
4233 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4235 (i->device == dev->device || in pci_dev_specific_reset()
4237 return i->reset(dev, probe); in pci_dev_specific_reset()
4243 static void quirk_dma_func0_alias(struct pci_dev *dev) in quirk_dma_func0_alias() argument
4245 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4246 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4261 static void quirk_dma_func1_alias(struct pci_dev *dev) in quirk_dma_func1_alias() argument
4263 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4264 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4351 static void quirk_fixed_dma_alias(struct pci_dev *dev) in quirk_fixed_dma_alias() argument
4355 id = pci_match_id(fixed_dma_alias_tbl, dev); in quirk_fixed_dma_alias()
4357 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4475 static void quirk_relaxedordering_disable(struct pci_dev *dev) in quirk_relaxedordering_disable() argument
4477 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4478 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); in quirk_relaxedordering_disable()
4592 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4659 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_amd_sb_acs() argument
4666 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4685 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) in pci_quirk_cavium_acs_match() argument
4687 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_cavium_acs_match()
4690 switch (dev->device) { in pci_quirk_cavium_acs_match()
4704 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_cavium_acs() argument
4706 if (!pci_quirk_cavium_acs_match(dev)) in pci_quirk_cavium_acs()
4721 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_xgene_acs() argument
4737 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_zhaoxin_pcie_ports_acs() argument
4739 if (!pci_is_pcie(dev) || in pci_quirk_zhaoxin_pcie_ports_acs()
4740 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && in pci_quirk_zhaoxin_pcie_ports_acs()
4741 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) in pci_quirk_zhaoxin_pcie_ports_acs()
4748 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4793 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) in pci_quirk_intel_pch_acs_match() argument
4798 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_intel_pch_acs_match()
4802 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4808 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_intel_pch_acs() argument
4810 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_intel_pch_acs()
4813 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4830 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_qcom_rp_acs() argument
4842 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_nxp_rp_acs() argument
4848 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_al_acs() argument
4850 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_al_acs()
4911 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) in pci_quirk_intel_spt_pch_acs_match() argument
4913 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pci_quirk_intel_spt_pch_acs_match()
4916 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4928 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_intel_spt_pch_acs() argument
4933 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_intel_spt_pch_acs()
4936 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4941 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_intel_spt_pch_acs()
4944 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_intel_spt_pch_acs()
4949 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_mf_endpoint_acs() argument
4965 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_rciep_acs() argument
4972 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) in pci_quirk_rciep_acs()
4979 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_brcm_acs() argument
5000 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) in pci_quirk_wangxun_nic_acs() argument
5002 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
5017 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
5181 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) in pci_dev_specific_acs_enabled() argument
5193 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5195 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5197 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5225 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_lpc_acs() argument
5235 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5257 pci_info(dev, "Disabling UPDCR peer decodes\n"); in pci_quirk_enable_intel_lpc_acs()
5272 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) in pci_quirk_enable_intel_rp_mpc_acs() argument
5282 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); in pci_quirk_enable_intel_rp_mpc_acs()
5284 pci_info(dev, "Enabling MPC IRBNCE\n"); in pci_quirk_enable_intel_rp_mpc_acs()
5286 pci_write_config_word(dev, INTEL_MPC_REG, mpc); in pci_quirk_enable_intel_rp_mpc_acs()
5297 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) in pci_quirk_enable_intel_pch_acs() argument
5299 if (!pci_quirk_intel_pch_acs_match(dev)) in pci_quirk_enable_intel_pch_acs()
5302 if (pci_quirk_enable_intel_lpc_acs(dev)) { in pci_quirk_enable_intel_pch_acs()
5303 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); in pci_quirk_enable_intel_pch_acs()
5307 pci_quirk_enable_intel_rp_mpc_acs(dev); in pci_quirk_enable_intel_pch_acs()
5309 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5311 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_pch_acs()
5316 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) in pci_quirk_enable_intel_spt_pch_acs() argument
5321 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_enable_intel_spt_pch_acs()
5324 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5328 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_enable_intel_spt_pch_acs()
5329 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_enable_intel_spt_pch_acs()
5336 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5339 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); in pci_quirk_enable_intel_spt_pch_acs()
5341 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); in pci_quirk_enable_intel_spt_pch_acs()
5346 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) in pci_quirk_disable_intel_spt_pch_acs_redir() argument
5351 if (!pci_quirk_intel_spt_pch_acs_match(dev)) in pci_quirk_disable_intel_spt_pch_acs_redir()
5354 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5358 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); in pci_quirk_disable_intel_spt_pch_acs_redir()
5359 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); in pci_quirk_disable_intel_spt_pch_acs_redir()
5363 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); in pci_quirk_disable_intel_spt_pch_acs_redir()
5365 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); in pci_quirk_disable_intel_spt_pch_acs_redir()
5373 int (*enable_acs)(struct pci_dev *dev);
5374 int (*disable_acs_redir)(struct pci_dev *dev);
5385 int pci_dev_specific_enable_acs(struct pci_dev *dev) in pci_dev_specific_enable_acs() argument
5392 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5394 (p->device == dev->device || in pci_dev_specific_enable_acs()
5397 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5406 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) in pci_dev_specific_disable_acs_redir() argument
5413 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5415 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5418 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5520 static void quirk_no_flr(struct pci_dev *dev) in quirk_no_flr() argument
5522 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5532 static void quirk_no_flr_snet(struct pci_dev *dev) in quirk_no_flr_snet() argument
5534 if (dev->revision == 0x1) in quirk_no_flr_snet()
5535 quirk_no_flr(dev); in quirk_no_flr_snet()
5660 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5668 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
6058 static void pci_fixup_no_d0_pme(struct pci_dev *dev) in pci_fixup_no_d0_pme() argument
6060 pci_info(dev, "PME# does not work under D0, disabling it\n"); in pci_fixup_no_d0_pme()
6061 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
6075 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) in pci_fixup_no_msi_no_pme() argument
6078 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); in pci_fixup_no_msi_no_pme()
6079 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
6081 pci_info(dev, "PME# is unreliable, disabling it\n"); in pci_fixup_no_msi_no_pme()
6082 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
6155 static void rom_bar_overlap_defect(struct pci_dev *dev) in rom_bar_overlap_defect() argument
6157 pci_info(dev, "working around ROM BAR overlap defect\n"); in rom_bar_overlap_defect()
6158 dev->rom_bar_overlap = 1; in rom_bar_overlap_defect()
6173 static void aspm_l1_acceptable_latency(struct pci_dev *dev) in aspm_l1_acceptable_latency() argument
6175 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); in aspm_l1_acceptable_latency()
6178 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); in aspm_l1_acceptable_latency()
6179 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", in aspm_l1_acceptable_latency()
6217 static void dpc_log_size(struct pci_dev *dev) in dpc_log_size() argument
6221 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); in dpc_log_size()
6225 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); in dpc_log_size()
6230 pci_info(dev, "Overriding RP PIO Log Size to 4\n"); in dpc_log_size()
6231 dev->dpc_rp_log_size = 4; in dpc_log_size()