20 #define MCU_FW_URB_MAX_PAYLOAD		0x3800
45 	u32 i, csum = 0;  in trace_mt_mcu_msg_send_cs()
47 	for (i = 0; i < skb->len / 4; i++)  in trace_mt_mcu_msg_send_cs()
98 			return 0;  in mt7601u_mcu_wait_resp()
117 	u8 seq = 0;  in mt7601u_mcu_msg_send()
121 		return 0;  in mt7601u_mcu_msg_send()
128 			seq = ++dev->mcu.msg_seq & 0xf;  in mt7601u_mcu_msg_send()
178 		return 0;  in mt7601u_mcu_tssi_read_kick()
189 	return 0;  in mt7601u_mcu_tssi_read_kick()
218 		return 0;  in mt7601u_write_reg_pairs()
227 	for (i = 0; i < cnt; i++) {  in mt7601u_write_reg_pairs()
247 		return 0;  in mt7601u_burst_write_regs()
257 	for (i = 0; i < cnt; i++)  in mt7601u_burst_write_regs()
298 	memset(buf.buf + sizeof(reg) + len, 0, 8);  in __mt7601u_dma_fw()
332 	return 0;  in __mt7601u_dma_fw()
341 	if (len == 0)  in mt7601u_dma_fw()
342 		return 0;  in mt7601u_dma_fw()
386 				     0x12, 0, ivb, sizeof(fw->ivb));  in mt7601u_upload_firmware()
387 	if (ret < 0)  in mt7601u_upload_firmware()
389 	ret = 0;  in mt7601u_upload_firmware()
441 		 (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf,  in mt7601u_load_firmware()
446 	mt7601u_wr(dev, 0x94c, 0);  in mt7601u_load_firmware()
447 	mt7601u_wr(dev, MT_FCE_PSE_CTRL, 0);  in mt7601u_load_firmware()
452 	mt7601u_wr(dev, 0xa44, 0);  in mt7601u_load_firmware()
453 	mt7601u_wr(dev, 0x230, 0x84210);  in mt7601u_load_firmware()
454 	mt7601u_wr(dev, 0x400, 0x80c00);  in mt7601u_load_firmware()
455 	mt7601u_wr(dev, 0x800, 1);  in mt7601u_load_firmware()
457 	mt7601u_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN |  in mt7601u_load_firmware()
471 	mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230);  in mt7601u_load_firmware()
475 	mt7601u_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44);  in mt7601u_load_firmware()
503 	return 0;  in mt7601u_mcu_init()
528 	return 0;  in mt7601u_mcu_cmd_init()