Lines Matching +full:10 +full:base +full:- +full:t1l
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
7 * Copyright (c) 2002-2003 TiVo Inc.
48 if (urb->actual_length < 8) in asix_status()
51 event = urb->transfer_buffer; in asix_status()
52 link = event->link & 0x01; in asix_status()
53 if (netif_carrier_ok(dev->net) != link) { in asix_status()
55 netdev_dbg(dev->net, "Link Status is: %d\n", link); in asix_status()
62 eth_hw_addr_set(dev->net, addr); in asix_set_netdev_dev_addr()
64 netdev_info(dev->net, "invalid hw address, using random\n"); in asix_set_netdev_dev_addr()
65 eth_hw_addr_random(dev->net); in asix_set_netdev_dev_addr()
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); in asix_get_phyid()
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); in asix_get_phyid()
104 return mii_link_ok(&dev->mii); in asix_get_link()
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); in asix_ioctl()
135 struct asix_data *data = (struct asix_data *)&dev->data; in ax88172_set_multicast()
138 if (net->flags & IFF_PROMISC) { in ax88172_set_multicast()
140 } else if (net->flags & IFF_ALLMULTI || in ax88172_set_multicast()
146 /* We use the 20 byte dev->data in ax88172_set_multicast()
153 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); in ax88172_set_multicast()
157 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; in ax88172_set_multicast()
158 data->multi_filter[crc_bits >> 3] |= in ax88172_set_multicast()
163 AX_MCAST_FILTER_SIZE, data->multi_filter); in ax88172_set_multicast()
176 mii_check_media(&dev->mii, 1, 1); in ax88172_link_reset()
177 mii_ethtool_gset(&dev->mii, &ecmd); in ax88172_link_reset()
183 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", in ax88172_link_reset()
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits); in asix_phy_reset()
214 while (timeout--) { in asix_phy_reset()
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR) in asix_phy_reset()
222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n", in asix_phy_reset()
223 dev->mii.phy_id); in asix_phy_reset()
231 unsigned long gpio_bits = dev->driver_info->data; in ax88172_bind()
236 for (i = 2; i >= 0; i--) { in ax88172_bind()
252 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n", in ax88172_bind()
260 dev->mii.dev = dev->net; in ax88172_bind()
261 dev->mii.mdio_read = asix_mdio_read; in ax88172_bind()
262 dev->mii.mdio_write = asix_mdio_write; in ax88172_bind()
263 dev->mii.phy_id_mask = 0x3f; in ax88172_bind()
264 dev->mii.reg_num_mask = 0x1f; in ax88172_bind()
266 dev->mii.phy_id = asix_read_phy_addr(dev, true); in ax88172_bind()
267 if (dev->mii.phy_id < 0) in ax88172_bind()
268 return dev->mii.phy_id; in ax88172_bind()
270 dev->net->netdev_ops = &ax88172_netdev_ops; in ax88172_bind()
271 dev->net->ethtool_ops = &ax88172_ethtool_ops; in ax88172_bind()
272 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ in ax88172_bind()
273 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ in ax88172_bind()
276 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, in ax88172_bind()
278 mii_nway_restart(&dev->mii); in ax88172_bind()
302 return -EOPNOTSUPP; in ax88772_ethtool_get_sset_count()
310 struct asix_common_private *priv = dev->driver_priv; in ax88772_ethtool_get_pauseparam()
312 phylink_ethtool_get_pauseparam(priv->phylink, pause); in ax88772_ethtool_get_pauseparam()
319 struct asix_common_private *priv = dev->driver_priv; in ax88772_ethtool_set_pauseparam()
321 return phylink_ethtool_set_pauseparam(priv->phylink, pause); in ax88772_ethtool_set_pauseparam()
346 struct asix_data *data = (struct asix_data *)&dev->data; in ax88772_reset()
347 struct asix_common_private *priv = dev->driver_priv; in ax88772_reset()
351 ether_addr_copy(data->mac_addr, dev->net->dev_addr); in ax88772_reset()
353 ETH_ALEN, data->mac_addr, 0); in ax88772_reset()
366 phylink_start(priv->phylink); in ax88772_reset()
376 struct asix_data *data = (struct asix_data *)&dev->data; in ax88772_hw_reset()
377 struct asix_common_private *priv = dev->driver_priv; in ax88772_hw_reset()
386 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy, in ax88772_hw_reset()
389 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); in ax88772_hw_reset()
393 if (priv->embd_phy) { in ax88772_hw_reset()
419 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772_hw_reset()
421 ret = -EIO; in ax88772_hw_reset()
437 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); in ax88772_hw_reset()
442 ether_addr_copy(data->mac_addr, dev->net->dev_addr); in ax88772_hw_reset()
444 ETH_ALEN, data->mac_addr, in_pm); in ax88772_hw_reset()
454 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", in ax88772_hw_reset()
458 netdev_dbg(dev->net, in ax88772_hw_reset()
470 struct asix_data *data = (struct asix_data *)&dev->data; in ax88772a_hw_reset()
471 struct asix_common_private *priv = dev->driver_priv; in ax88772a_hw_reset()
479 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy | in ax88772a_hw_reset()
482 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); in ax88772a_hw_reset()
509 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
511 ret = -1; in ax88772a_hw_reset()
515 if (priv->chipcode == AX_AX88772B_CHIPCODE) { in ax88772a_hw_reset()
519 netdev_dbg(dev->net, "Write BQ setting failed: %d\n", in ax88772a_hw_reset()
523 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) { in ax88772a_hw_reset()
525 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
527 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
529 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
532 netdev_dbg(dev->net, in ax88772a_hw_reset()
538 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
542 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
546 asix_mdio_write_nopm(dev->net, dev->mii.phy_id, in ax88772a_hw_reset()
555 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); in ax88772a_hw_reset()
560 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); in ax88772a_hw_reset()
562 data->mac_addr, in_pm); in ax88772a_hw_reset()
581 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", in ax88772a_hw_reset()
585 netdev_dbg(dev->net, in ax88772a_hw_reset()
610 struct asix_common_private *priv = dev->driver_priv; in ax88772_suspend()
613 if (netif_running(dev->net)) { in ax88772_suspend()
615 phylink_suspend(priv->phylink, false); in ax88772_suspend()
624 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n", in ax88772_suspend()
631 struct asix_common_private *priv = dev->driver_priv; in asix_suspend()
633 if (priv && priv->suspend) in asix_suspend()
634 priv->suspend(dev); in asix_suspend()
641 struct asix_common_private *priv = dev->driver_priv; in ax88772_resume()
645 if (!priv->reset(dev, 1)) in ax88772_resume()
648 if (netif_running(dev->net)) { in ax88772_resume()
650 phylink_resume(priv->phylink); in ax88772_resume()
658 struct asix_common_private *priv = dev->driver_priv; in asix_resume()
660 if (priv && priv->resume) in asix_resume()
661 priv->resume(dev); in asix_resume()
668 struct asix_common_private *priv = dev->driver_priv; in ax88772_init_mdio()
671 priv->mdio = mdiobus_alloc(); in ax88772_init_mdio()
672 if (!priv->mdio) in ax88772_init_mdio()
673 return -ENOMEM; in ax88772_init_mdio()
675 priv->mdio->priv = dev; in ax88772_init_mdio()
676 priv->mdio->read = &asix_mdio_bus_read; in ax88772_init_mdio()
677 priv->mdio->write = &asix_mdio_bus_write; in ax88772_init_mdio()
678 priv->mdio->name = "Asix MDIO Bus"; in ax88772_init_mdio()
679 /* mii bus name is usb-<usb bus number>-<usb device number> */ in ax88772_init_mdio()
680 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d", in ax88772_init_mdio()
681 dev->udev->bus->busnum, dev->udev->devnum); in ax88772_init_mdio()
683 ret = mdiobus_register(priv->mdio); in ax88772_init_mdio()
685 netdev_err(dev->net, "Could not register MDIO bus (err %d)\n", ret); in ax88772_init_mdio()
686 mdiobus_free(priv->mdio); in ax88772_init_mdio()
687 priv->mdio = NULL; in ax88772_init_mdio()
695 mdiobus_unregister(priv->mdio); in ax88772_mdio_unregister()
696 mdiobus_free(priv->mdio); in ax88772_mdio_unregister()
701 struct asix_common_private *priv = dev->driver_priv; in ax88772_init_phy()
704 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr); in ax88772_init_phy()
705 if (!priv->phydev) { in ax88772_init_phy()
706 netdev_err(dev->net, "Could not find PHY\n"); in ax88772_init_phy()
707 return -ENODEV; in ax88772_init_phy()
710 ret = phylink_connect_phy(priv->phylink, priv->phydev); in ax88772_init_phy()
712 netdev_err(dev->net, "Could not connect PHY\n"); in ax88772_init_phy()
716 phy_suspend(priv->phydev); in ax88772_init_phy()
717 priv->phydev->mac_managed_pm = true; in ax88772_init_phy()
719 phy_attached_info(priv->phydev); in ax88772_init_phy()
721 if (priv->embd_phy) in ax88772_init_phy()
728 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR); in ax88772_init_phy()
729 if (!priv->phydev_int) { in ax88772_init_phy()
731 phylink_disconnect_phy(priv->phylink); in ax88772_init_phy()
733 netdev_err(dev->net, "Could not find internal PHY\n"); in ax88772_init_phy()
734 return -ENODEV; in ax88772_init_phy()
737 priv->phydev_int->mac_managed_pm = true; in ax88772_init_phy()
738 phy_suspend(priv->phydev_int); in ax88772_init_phy()
752 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); in ax88772_mac_link_down()
764 struct usbnet *dev = netdev_priv(to_net_dev(config->dev)); in ax88772_mac_link_up()
797 struct asix_common_private *priv = dev->driver_priv; in ax88772_phylink_setup()
801 priv->phylink_config.dev = &dev->net->dev; in ax88772_phylink_setup()
802 priv->phylink_config.type = PHYLINK_NETDEV; in ax88772_phylink_setup()
803 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | in ax88772_phylink_setup()
807 priv->phylink_config.supported_interfaces); in ax88772_phylink_setup()
809 priv->phylink_config.supported_interfaces); in ax88772_phylink_setup()
811 if (priv->embd_phy) in ax88772_phylink_setup()
816 phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode, in ax88772_phylink_setup()
821 priv->phylink = phylink; in ax88772_phylink_setup()
831 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL); in ax88772_bind()
833 return -ENOMEM; in ax88772_bind()
835 dev->driver_priv = priv; in ax88772_bind()
840 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) { in ax88772_bind()
841 netif_dbg(dev, ifup, dev->net, in ax88772_bind()
845 if (dev->driver_info->data & FLAG_EEPROM_MAC) { in ax88772_bind()
859 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", in ax88772_bind()
867 dev->net->netdev_ops = &ax88772_netdev_ops; in ax88772_bind()
868 dev->net->ethtool_ops = &ax88772_ethtool_ops; in ax88772_bind()
869 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */ in ax88772_bind()
870 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */ in ax88772_bind()
876 priv->phy_addr = ret; in ax88772_bind()
877 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR); in ax88772_bind()
880 &priv->chipcode, 0); in ax88772_bind()
882 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret); in ax88772_bind()
886 priv->chipcode &= AX_CHIPCODE_MASK; in ax88772_bind()
888 priv->resume = ax88772_resume; in ax88772_bind()
889 priv->suspend = ax88772_suspend; in ax88772_bind()
890 if (priv->chipcode == AX_AX88772_CHIPCODE) in ax88772_bind()
891 priv->reset = ax88772_hw_reset; in ax88772_bind()
893 priv->reset = ax88772a_hw_reset; in ax88772_bind()
895 ret = priv->reset(dev, 0); in ax88772_bind()
897 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret); in ax88772_bind()
902 if (dev->driver_info->flags & FLAG_FRAMING_AX) { in ax88772_bind()
903 /* hard_mtu is still the default - the device does not support in ax88772_bind()
905 dev->rx_urb_size = 2048; in ax88772_bind()
908 priv->presvd_phy_bmcr = 0; in ax88772_bind()
909 priv->presvd_phy_advertise = 0; in ax88772_bind()
926 phylink_destroy(priv->phylink); in ax88772_bind()
935 struct asix_common_private *priv = dev->driver_priv; in ax88772_stop()
937 phylink_stop(priv->phylink); in ax88772_stop()
944 struct asix_common_private *priv = dev->driver_priv; in ax88772_unbind()
947 phylink_disconnect_phy(priv->phylink); in ax88772_unbind()
949 phylink_destroy(priv->phylink); in ax88772_unbind()
951 asix_rx_fixup_common_free(dev->driver_priv); in ax88772_unbind()
956 asix_rx_fixup_common_free(dev->driver_priv); in ax88178_unbind()
957 kfree(dev->driver_priv); in ax88178_unbind()
977 struct asix_data *data = (struct asix_data *)&dev->data; in marvell_phy_init()
980 netdev_dbg(dev->net, "marvell_phy_init()\n"); in marvell_phy_init()
982 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); in marvell_phy_init()
983 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg); in marvell_phy_init()
985 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, in marvell_phy_init()
988 if (data->ledmode) { in marvell_phy_init()
989 reg = asix_mdio_read(dev->net, dev->mii.phy_id, in marvell_phy_init()
991 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg); in marvell_phy_init()
995 asix_mdio_write(dev->net, dev->mii.phy_id, in marvell_phy_init()
998 reg = asix_mdio_read(dev->net, dev->mii.phy_id, in marvell_phy_init()
1000 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg); in marvell_phy_init()
1008 struct asix_data *data = (struct asix_data *)&dev->data; in rtl8211cl_phy_init()
1010 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n"); in rtl8211cl_phy_init()
1012 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005); in rtl8211cl_phy_init()
1013 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0); in rtl8211cl_phy_init()
1014 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01, in rtl8211cl_phy_init()
1015 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080); in rtl8211cl_phy_init()
1016 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); in rtl8211cl_phy_init()
1018 if (data->ledmode == 12) { in rtl8211cl_phy_init()
1019 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002); in rtl8211cl_phy_init()
1020 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb); in rtl8211cl_phy_init()
1021 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0); in rtl8211cl_phy_init()
1029 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); in marvell_led_status()
1031 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg); in marvell_led_status()
1033 /* Clear out the center LED bits - 0x03F0 */ in marvell_led_status()
1047 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg); in marvell_led_status()
1048 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); in marvell_led_status()
1055 struct asix_data *data = (struct asix_data *)&dev->data; in ax88178_reset()
1064 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret); in ax88178_reset()
1068 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status); in ax88178_reset()
1073 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret); in ax88178_reset()
1079 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom); in ax88178_reset()
1082 data->phymode = PHY_MODE_MARVELL; in ax88178_reset()
1083 data->ledmode = 0; in ax88178_reset()
1086 data->phymode = le16_to_cpu(eeprom) & 0x7F; in ax88178_reset()
1087 data->ledmode = le16_to_cpu(eeprom) >> 8; in ax88178_reset()
1090 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode); in ax88178_reset()
1100 netdev_dbg(dev->net, "gpio phymode == 1 path\n"); in ax88178_reset()
1107 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); in ax88178_reset()
1120 if (data->phymode == PHY_MODE_MARVELL) { in ax88178_reset()
1123 } else if (data->phymode == PHY_MODE_RTL8211CL) in ax88178_reset()
1127 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, in ax88178_reset()
1129 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, in ax88178_reset()
1133 mii_nway_restart(&dev->mii); in ax88178_reset()
1136 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); in ax88178_reset()
1138 data->mac_addr, 0); in ax88178_reset()
1153 struct asix_data *data = (struct asix_data *)&dev->data; in ax88178_link_reset()
1156 netdev_dbg(dev->net, "ax88178_link_reset()\n"); in ax88178_link_reset()
1158 mii_check_media(&dev->mii, 1, 1); in ax88178_link_reset()
1159 mii_ethtool_gset(&dev->mii, &ecmd); in ax88178_link_reset()
1177 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n", in ax88178_link_reset()
1182 if (data->phymode == PHY_MODE_MARVELL && data->ledmode) in ax88178_link_reset()
1193 int old_rx_urb_size = dev->rx_urb_size; in ax88178_set_mfb()
1195 if (dev->hard_mtu < 2048) { in ax88178_set_mfb()
1196 dev->rx_urb_size = 2048; in ax88178_set_mfb()
1198 } else if (dev->hard_mtu < 4096) { in ax88178_set_mfb()
1199 dev->rx_urb_size = 4096; in ax88178_set_mfb()
1201 } else if (dev->hard_mtu < 8192) { in ax88178_set_mfb()
1202 dev->rx_urb_size = 8192; in ax88178_set_mfb()
1204 } else if (dev->hard_mtu < 16384) { in ax88178_set_mfb()
1205 dev->rx_urb_size = 16384; in ax88178_set_mfb()
1213 if (dev->net->mtu > 1500) in ax88178_set_mfb()
1219 if (dev->rx_urb_size > old_rx_urb_size) in ax88178_set_mfb()
1226 int ll_mtu = new_mtu + net->hard_header_len + 4; in ax88178_change_mtu()
1228 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu); in ax88178_change_mtu()
1230 if ((ll_mtu % dev->maxpacket) == 0) in ax88178_change_mtu()
1231 return -EDOM; in ax88178_change_mtu()
1233 net->mtu = new_mtu; in ax88178_change_mtu()
1234 dev->hard_mtu = net->mtu + net->hard_header_len; in ax88178_change_mtu()
1266 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); in ax88178_bind()
1273 dev->mii.dev = dev->net; in ax88178_bind()
1274 dev->mii.mdio_read = asix_mdio_read; in ax88178_bind()
1275 dev->mii.mdio_write = asix_mdio_write; in ax88178_bind()
1276 dev->mii.phy_id_mask = 0x1f; in ax88178_bind()
1277 dev->mii.reg_num_mask = 0xff; in ax88178_bind()
1278 dev->mii.supports_gmii = 1; in ax88178_bind()
1280 dev->mii.phy_id = asix_read_phy_addr(dev, true); in ax88178_bind()
1281 if (dev->mii.phy_id < 0) in ax88178_bind()
1282 return dev->mii.phy_id; in ax88178_bind()
1284 dev->net->netdev_ops = &ax88178_netdev_ops; in ax88178_bind()
1285 dev->net->ethtool_ops = &ax88178_ethtool_ops; in ax88178_bind()
1286 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4); in ax88178_bind()
1296 if (dev->driver_info->flags & FLAG_FRAMING_AX) { in ax88178_bind()
1297 /* hard_mtu is still the default - the device does not support in ax88178_bind()
1299 dev->rx_urb_size = 2048; in ax88178_bind()
1302 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL); in ax88178_bind()
1303 if (!dev->driver_priv) in ax88178_bind()
1304 return -ENOMEM; in ax88178_bind()
1320 .description = "DLink DUB-E100 USB Ethernet",
1330 .description = "Netgear FA-120 USB Ethernet",
1376 .description = "Linux Automation GmbH USB 10Base-T1L",
1404 * no-name packaging.
1434 // DLink DUB-E100
1442 // Hawking UF200, TrendNet TU2-ET100
1450 // Billionton Systems, GUSB2AM-1G-B
1458 // Buffalo LUA-U2-KTX
1462 // Buffalo LUA-U2-GT 10/100/1000
1466 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1470 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1474 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1478 // corega FEther USB2-TX
1482 // Surecom EP-1427X-2
1490 // JVC MP-PRX1 Port Replicator
1494 // Lenovo U2L100P 10/100
1498 // ASIX AX88772B 10/100
1502 // ASIX AX88772 10/100
1506 // ASIX AX88178 10/100/1000
1510 // Logitec LAN-GTJ/U2A
1522 // DLink DUB-E100 H/W Ver B1
1526 // DLink DUB-E100 H/W Ver B1 Alternate
1530 // DLink DUB-E100 H/W Ver C1
1538 // IO-DATA ETG-US2
1550 // Cables-to-Go USB Ethernet Adapter
1578 // Linux Automation GmbH USB 10Base-T1L