318 				  const struct nxp_c45_reg_field *reg_field)  in nxp_c45_read_reg_field()  argument
323 	if (reg_field->size == 0) {  in nxp_c45_read_reg_field()
328 	ret = phy_read_mmd(phydev, reg_field->devad, reg_field->reg);  in nxp_c45_read_reg_field()
332 	mask = reg_field->size == 1 ? BIT(reg_field->offset) :  in nxp_c45_read_reg_field()
333 		GENMASK(reg_field->offset + reg_field->size - 1,  in nxp_c45_read_reg_field()
334 			reg_field->offset);  in nxp_c45_read_reg_field()
336 	ret >>= reg_field->offset;  in nxp_c45_read_reg_field()
342 				   const struct nxp_c45_reg_field *reg_field,  in nxp_c45_write_reg_field()  argument
348 	if (reg_field->size == 0) {  in nxp_c45_write_reg_field()
353 	mask = reg_field->size == 1 ? BIT(reg_field->offset) :  in nxp_c45_write_reg_field()
354 		GENMASK(reg_field->offset + reg_field->size - 1,  in nxp_c45_write_reg_field()
355 			reg_field->offset);  in nxp_c45_write_reg_field()
356 	set = val << reg_field->offset;  in nxp_c45_write_reg_field()
358 	return phy_modify_mmd_changed(phydev, reg_field->devad,  in nxp_c45_write_reg_field()
359 				      reg_field->reg, mask, set);  in nxp_c45_write_reg_field()
363 				 const struct nxp_c45_reg_field *reg_field)  in nxp_c45_set_reg_field()  argument
365 	if (reg_field->size != 1) {  in nxp_c45_set_reg_field()
370 	return nxp_c45_write_reg_field(phydev, reg_field, 1);  in nxp_c45_set_reg_field()
374 				   const struct nxp_c45_reg_field *reg_field)  in nxp_c45_clear_reg_field()  argument
376 	if (reg_field->size != 1) {  in nxp_c45_clear_reg_field()
381 	return nxp_c45_write_reg_field(phydev, reg_field, 0);  in nxp_c45_clear_reg_field()
1175 	const struct nxp_c45_reg_field *reg_field;  in nxp_c45_get_stats()  local
1182 			reg_field = &common_hw_stats[i].counter;  in nxp_c45_get_stats()
1185 			reg_field = &phy_data->stats[idx].counter;  in nxp_c45_get_stats()
1188 		ret = nxp_c45_read_reg_field(phydev, reg_field);  in nxp_c45_get_stats()