Lines Matching +full:0 +full:x17a0
103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
128 return 0; in vsc85xx_get_sset_count()
141 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()
153 if (val < 0) in vsc85xx_get_stat()
171 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_stats()
202 return 0; in vsc85xx_mdix_get()
224 reg_val = 0; in vsc85xx_mdix_set()
234 if (rc < 0) in vsc85xx_mdix_set()
246 if (reg_val < 0) in vsc85xx_downshift_get()
255 return 0; in vsc85xx_downshift_get()
261 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ in vsc85xx_downshift_set()
283 u16 pwd[3] = {0, 0, 0}; in vsc85xx_wol_set()
287 if (rc < 0) in vsc85xx_wol_set()
292 for (i = 0; i < ARRAY_SIZE(pwd); i++) in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
305 for (i = 0; i < ARRAY_SIZE(pwd); i++) in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
325 if (rc < 0) in vsc85xx_wol_set()
346 return 0; in vsc85xx_wol_set()
355 u16 pwd[3] = {0, 0, 0}; in vsc85xx_wol_get()
359 if (rc < 0) in vsc85xx_wol_get()
366 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
369 for (i = 0; i < ARRAY_SIZE(pwd); i++) { in vsc85xx_wol_get()
370 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; in vsc85xx_wol_get()
371 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) in vsc85xx_wol_get()
377 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
387 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); in vsc85xx_edge_rate_magic_get()
396 sd = 0; in vsc85xx_edge_rate_magic_get()
398 for (i = 0; i < ARRAY_SIZE(edge_table); i++) in vsc85xx_edge_rate_magic_get()
400 for (j = 0; j < sd_array_size; j++) in vsc85xx_edge_rate_magic_get()
433 return 0; in vsc85xx_edge_rate_magic_get()
451 for (i = 0; i < priv->nleds; i++) { in vsc85xx_dt_led_modes_get()
453 if (ret < 0) in vsc85xx_dt_led_modes_get()
458 if (ret < 0) in vsc85xx_dt_led_modes_get()
463 return 0; in vsc85xx_dt_led_modes_get()
533 u16 reg_val = 0; in vsc85xx_update_rgmii_cntl()
534 u16 mask = 0; in vsc85xx_update_rgmii_cntl()
537 int rc = 0; in vsc85xx_update_rgmii_cntl()
553 if (rx_delay < 0) { in vsc85xx_update_rgmii_cntl()
563 if (tx_delay < 0) { in vsc85xx_update_rgmii_cntl()
617 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
625 {0x0f90, 0x00688980}, in vsc8531_pre_init_seq_set()
626 {0x0696, 0x00000003}, in vsc8531_pre_init_seq_set()
627 {0x07fa, 0x0050100f}, in vsc8531_pre_init_seq_set()
628 {0x1686, 0x00000004}, in vsc8531_pre_init_seq_set()
636 if (rc < 0) in vsc8531_pre_init_seq_set()
639 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); in vsc8531_pre_init_seq_set()
640 if (rc < 0) in vsc8531_pre_init_seq_set()
643 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); in vsc8531_pre_init_seq_set()
644 if (rc < 0) in vsc8531_pre_init_seq_set()
648 if (rc < 0) in vsc8531_pre_init_seq_set()
653 if (oldpage < 0) in vsc8531_pre_init_seq_set()
656 for (i = 0; i < ARRAY_SIZE(init_seq); i++) in vsc8531_pre_init_seq_set()
669 {0x0f82, 0x0012b00a}, in vsc85xx_eee_init_seq_set()
670 {0x1686, 0x00000004}, in vsc85xx_eee_init_seq_set()
671 {0x168c, 0x00d2c46f}, in vsc85xx_eee_init_seq_set()
672 {0x17a2, 0x00000620}, in vsc85xx_eee_init_seq_set()
673 {0x16a0, 0x00eeffdd}, in vsc85xx_eee_init_seq_set()
674 {0x16a6, 0x00071448}, in vsc85xx_eee_init_seq_set()
675 {0x16a4, 0x0013132f}, in vsc85xx_eee_init_seq_set()
676 {0x16a8, 0x00000000}, in vsc85xx_eee_init_seq_set()
677 {0x0ffc, 0x00c0a028}, in vsc85xx_eee_init_seq_set()
678 {0x0fe8, 0x0091b06c}, in vsc85xx_eee_init_seq_set()
679 {0x0fea, 0x00041600}, in vsc85xx_eee_init_seq_set()
680 {0x0f80, 0x00000af4}, in vsc85xx_eee_init_seq_set()
681 {0x0fec, 0x00901809}, in vsc85xx_eee_init_seq_set()
682 {0x0fee, 0x0000a6a1}, in vsc85xx_eee_init_seq_set()
683 {0x0ffe, 0x00b01007}, in vsc85xx_eee_init_seq_set()
684 {0x16b0, 0x00eeff00}, in vsc85xx_eee_init_seq_set()
685 {0x16b2, 0x00007000}, in vsc85xx_eee_init_seq_set()
686 {0x16b4, 0x00000814}, in vsc85xx_eee_init_seq_set()
693 if (oldpage < 0) in vsc85xx_eee_init_seq_set()
696 for (i = 0; i < ARRAY_SIZE(init_eee); i++) in vsc85xx_eee_init_seq_set()
739 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 in vsc85xx_csr_read()
740 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. in vsc85xx_csr_read()
747 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) in vsc85xx_csr_read()
749 target &= 0x3; in vsc85xx_csr_read()
751 target = 0; in vsc85xx_csr_read()
768 return 0xffffffff; in vsc85xx_csr_read()
792 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 in vsc85xx_csr_write()
793 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. in vsc85xx_csr_write()
806 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) in vsc85xx_csr_write()
808 target &= 0x3; in vsc85xx_csr_write()
810 target = 0; in vsc85xx_csr_write()
832 return 0; in vsc85xx_csr_write()
839 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
869 return 0; in vsc8584_cmd()
902 return 0; in vsc8584_micro_deassert_reset()
922 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
923 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
936 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | in vsc8584_micro_assert_reset()
945 return 0; in vsc8584_micro_assert_reset()
998 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
1000 for (i = 0; i < fw->size; i++) in vsc8584_patch_fw()
1009 return 0; in vsc8584_patch_fw()
1022 if (reg != 0x3eb7) { in vsc8574_is_serdes_init()
1028 if (reg != 0x4012) { in vsc8574_is_serdes_init()
1057 {0x0fae, 0x000401bd}, in vsc8574_config_pre_init()
1058 {0x0fac, 0x000f000f}, in vsc8574_config_pre_init()
1059 {0x17a0, 0x00a0f147}, in vsc8574_config_pre_init()
1060 {0x0fe4, 0x00052f54}, in vsc8574_config_pre_init()
1061 {0x1792, 0x0027303d}, in vsc8574_config_pre_init()
1062 {0x07fe, 0x00000704}, in vsc8574_config_pre_init()
1063 {0x0fe0, 0x00060150}, in vsc8574_config_pre_init()
1064 {0x0f82, 0x0012b00a}, in vsc8574_config_pre_init()
1065 {0x0f80, 0x00000d74}, in vsc8574_config_pre_init()
1066 {0x02e0, 0x00000012}, in vsc8574_config_pre_init()
1067 {0x03a2, 0x00050208}, in vsc8574_config_pre_init()
1068 {0x03b2, 0x00009186}, in vsc8574_config_pre_init()
1069 {0x0fb0, 0x000e3700}, in vsc8574_config_pre_init()
1070 {0x1688, 0x00049f81}, in vsc8574_config_pre_init()
1071 {0x0fd2, 0x0000ffff}, in vsc8574_config_pre_init()
1072 {0x168a, 0x00039fa2}, in vsc8574_config_pre_init()
1073 {0x1690, 0x0020640b}, in vsc8574_config_pre_init()
1074 {0x0258, 0x00002220}, in vsc8574_config_pre_init()
1075 {0x025a, 0x00002a20}, in vsc8574_config_pre_init()
1076 {0x025c, 0x00003060}, in vsc8574_config_pre_init()
1077 {0x025e, 0x00003fa0}, in vsc8574_config_pre_init()
1078 {0x03a6, 0x0000e0f0}, in vsc8574_config_pre_init()
1079 {0x0f92, 0x00001489}, in vsc8574_config_pre_init()
1080 {0x16a2, 0x00007000}, in vsc8574_config_pre_init()
1081 {0x16a6, 0x00071448}, in vsc8574_config_pre_init()
1082 {0x16a0, 0x00eeffdd}, in vsc8574_config_pre_init()
1083 {0x0fe8, 0x0091b06c}, in vsc8574_config_pre_init()
1084 {0x0fea, 0x00041600}, in vsc8574_config_pre_init()
1085 {0x16b0, 0x00eeff00}, in vsc8574_config_pre_init()
1086 {0x16b2, 0x00007000}, in vsc8574_config_pre_init()
1087 {0x16b4, 0x00000814}, in vsc8574_config_pre_init()
1088 {0x0f90, 0x00688980}, in vsc8574_config_pre_init()
1089 {0x03a4, 0x0000d8f0}, in vsc8574_config_pre_init()
1090 {0x0fc0, 0x00000400}, in vsc8574_config_pre_init()
1091 {0x07fa, 0x0050100f}, in vsc8574_config_pre_init()
1092 {0x0796, 0x00000003}, in vsc8574_config_pre_init()
1093 {0x07f8, 0x00c3ff98}, in vsc8574_config_pre_init()
1094 {0x0fa4, 0x0018292a}, in vsc8574_config_pre_init()
1095 {0x168c, 0x00d2c46f}, in vsc8574_config_pre_init()
1096 {0x17a2, 0x00000620}, in vsc8574_config_pre_init()
1097 {0x16a4, 0x0013132f}, in vsc8574_config_pre_init()
1098 {0x16a8, 0x00000000}, in vsc8574_config_pre_init()
1099 {0x0ffc, 0x00c0a028}, in vsc8574_config_pre_init()
1100 {0x0fec, 0x00901c09}, in vsc8574_config_pre_init()
1101 {0x0fee, 0x0004a6a1}, in vsc8574_config_pre_init()
1102 {0x0ffe, 0x00b01807}, in vsc8574_config_pre_init()
1105 {0x0486, 0x0008a518}, in vsc8574_config_pre_init()
1106 {0x0488, 0x006dc696}, in vsc8574_config_pre_init()
1107 {0x048a, 0x00000912}, in vsc8574_config_pre_init()
1108 {0x048e, 0x00000db6}, in vsc8574_config_pre_init()
1109 {0x049c, 0x00596596}, in vsc8574_config_pre_init()
1110 {0x049e, 0x00000514}, in vsc8574_config_pre_init()
1111 {0x04a2, 0x00410280}, in vsc8574_config_pre_init()
1112 {0x04a4, 0x00000000}, in vsc8574_config_pre_init()
1113 {0x04a6, 0x00000000}, in vsc8574_config_pre_init()
1114 {0x04a8, 0x00000000}, in vsc8574_config_pre_init()
1115 {0x04aa, 0x00000000}, in vsc8574_config_pre_init()
1116 {0x04ae, 0x007df7dd}, in vsc8574_config_pre_init()
1117 {0x04b0, 0x006d95d4}, in vsc8574_config_pre_init()
1118 {0x04b2, 0x00492410}, in vsc8574_config_pre_init()
1134 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1141 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1145 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1146 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1147 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1148 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1156 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8574_config_pre_init()
1161 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1165 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) in vsc8574_config_pre_init()
1221 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1222 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1272 u32 rd_dat = 0; in vsc8584_mcb_rd_trig()
1276 (0x40000000 | (1L << mcb_slave_num))); in vsc8584_mcb_rd_trig()
1279 !(rd_dat & 0x40000000), in vsc8584_mcb_rd_trig()
1280 4000, 200000, 0, in vsc8584_mcb_rd_trig()
1289 u32 rd_dat = 0; in vsc8584_mcb_wr_trig()
1293 (0x80000000 | (1L << mcb_slave_num))); in vsc8584_mcb_wr_trig()
1296 !(rd_dat & 0x80000000), in vsc8584_mcb_wr_trig()
1297 4000, 200000, 0, in vsc8584_mcb_wr_trig()
1305 int ret = 0; in vsc8584_pll5g_reset()
1307 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1308 if (ret < 0) in vsc8584_pll5g_reset()
1316 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1317 if (ret < 0) in vsc8584_pll5g_reset()
1324 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1325 if (ret < 0) in vsc8584_pll5g_reset()
1327 dis_fsm = 0; in vsc8584_pll5g_reset()
1333 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1334 if (ret < 0) in vsc8584_pll5g_reset()
1346 {0x07fa, 0x0050100f}, in vsc8584_config_pre_init()
1347 {0x1688, 0x00049f81}, in vsc8584_config_pre_init()
1348 {0x0f90, 0x00688980}, in vsc8584_config_pre_init()
1349 {0x03a4, 0x0000d8f0}, in vsc8584_config_pre_init()
1350 {0x0fc0, 0x00000400}, in vsc8584_config_pre_init()
1351 {0x0f82, 0x0012b002}, in vsc8584_config_pre_init()
1352 {0x1686, 0x00000004}, in vsc8584_config_pre_init()
1353 {0x168c, 0x00d2c46f}, in vsc8584_config_pre_init()
1354 {0x17a2, 0x00000620}, in vsc8584_config_pre_init()
1355 {0x16a0, 0x00eeffdd}, in vsc8584_config_pre_init()
1356 {0x16a6, 0x00071448}, in vsc8584_config_pre_init()
1357 {0x16a4, 0x0013132f}, in vsc8584_config_pre_init()
1358 {0x16a8, 0x00000000}, in vsc8584_config_pre_init()
1359 {0x0ffc, 0x00c0a028}, in vsc8584_config_pre_init()
1360 {0x0fe8, 0x0091b06c}, in vsc8584_config_pre_init()
1361 {0x0fea, 0x00041600}, in vsc8584_config_pre_init()
1362 {0x0f80, 0x00fffaff}, in vsc8584_config_pre_init()
1363 {0x0fec, 0x00901809}, in vsc8584_config_pre_init()
1364 {0x0ffe, 0x00b01007}, in vsc8584_config_pre_init()
1365 {0x16b0, 0x00eeff00}, in vsc8584_config_pre_init()
1366 {0x16b2, 0x00007000}, in vsc8584_config_pre_init()
1367 {0x16b4, 0x00000814}, in vsc8584_config_pre_init()
1370 {0x0486, 0x0008a518}, in vsc8584_config_pre_init()
1371 {0x0488, 0x006dc696}, in vsc8584_config_pre_init()
1372 {0x048a, 0x00000912}, in vsc8584_config_pre_init()
1381 if (ret < 0) { in vsc8584_config_pre_init()
1393 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1406 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1410 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1418 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1421 reg &= ~0x007f; in vsc8584_config_pre_init()
1422 reg |= 0x0019; in vsc8584_config_pre_init()
1425 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1427 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8584_config_pre_init()
1432 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1436 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) in vsc8584_config_pre_init()
1490 /* Write patch vector 0, to skip IB cal polling */ in vsc8584_config_pre_init()
1492 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */ in vsc8584_config_pre_init()
1497 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */ in vsc8584_config_pre_init()
1503 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ in vsc8584_config_pre_init()
1566 /* Enable output (mode=0) and write zero to it */ in vsc85xx_coma_mode_release()
1569 MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0); in vsc85xx_coma_mode_release()
1718 * accessed via the PHY whose internal address in the package is 0. in vsc8584_config_init()
1728 * nibble of the phy_id_mask is always 0. This works because in vsc8584_config_init()
1729 * the lowest nibble of the PHY_ID's below are also 0. in vsc8584_config_init()
1731 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1794 for (i = 0; i < vsc8531->nleds; i++) { in vsc8584_config_init()
1800 return 0; in vsc8584_config_init()
1813 if (irq_status < 0) in vsc8584_handle_interrupt()
1817 * irq_status would be 0. in vsc8584_handle_interrupt()
1861 for (i = 0; i < vsc8531->nleds; i++) { in vsc85xx_config_init()
1867 return 0; in vsc85xx_config_init()
1887 if (val == 0xffffffff) in __phy_write_mcb_s6g()
1895 return 0; in __phy_write_mcb_s6g()
1949 * 2. disable patch vector 0, in order to allow IB cal poll during FoJi in vsc8514_config_host_serdes()
1955 /* clear bit 8, to disable patch vector 0 */ in vsc8514_config_host_serdes()
1971 {0x0f90, 0x00688980}, in vsc8514_config_pre_init()
1972 {0x0786, 0x00000003}, in vsc8514_config_pre_init()
1973 {0x07fa, 0x0050100f}, in vsc8514_config_pre_init()
1974 {0x0f82, 0x0012b002}, in vsc8514_config_pre_init()
1975 {0x1686, 0x00000004}, in vsc8514_config_pre_init()
1976 {0x168c, 0x00d2c46f}, in vsc8514_config_pre_init()
1977 {0x17a2, 0x00000620}, in vsc8514_config_pre_init()
1978 {0x16a0, 0x00eeffdd}, in vsc8514_config_pre_init()
1979 {0x16a6, 0x00071448}, in vsc8514_config_pre_init()
1980 {0x16a4, 0x0013132f}, in vsc8514_config_pre_init()
1981 {0x16a8, 0x00000000}, in vsc8514_config_pre_init()
1982 {0x0ffc, 0x00c0a028}, in vsc8514_config_pre_init()
1983 {0x0fe8, 0x0091b06c}, in vsc8514_config_pre_init()
1984 {0x0fea, 0x00041600}, in vsc8514_config_pre_init()
1985 {0x0f80, 0x00fffaff}, in vsc8514_config_pre_init()
1986 {0x0fec, 0x00901809}, in vsc8514_config_pre_init()
1987 {0x0ffe, 0x00b01007}, in vsc8514_config_pre_init()
1988 {0x16b0, 0x00eeff00}, in vsc8514_config_pre_init()
1989 {0x16b2, 0x00007000}, in vsc8514_config_pre_init()
1990 {0x16b4, 0x00000814}, in vsc8514_config_pre_init()
1998 if (ret < 0) { in vsc8514_config_pre_init()
2018 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8514_config_pre_init()
2036 * 2. write patch vector 0, to skip IB cal polling executed in vsc8514_config_pre_init()
2037 * as part of the 0x80E0 ROM command in vsc8514_config_pre_init()
2044 /* ROM address to trap, for patch vector 0 */ in vsc8514_config_pre_init()
2049 /* RAM address to jump to, when patch vector 0 enabled */ in vsc8514_config_pre_init()
2055 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */ in vsc8514_config_pre_init()
2114 for (i = 0; i < vsc8531->nleds; i++) { in vsc8514_config_init()
2129 int rc = 0; in vsc85xx_ack_interrupt()
2134 return (rc < 0) ? rc : 0; in vsc85xx_ack_interrupt()
2152 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2153 if (rc < 0) in vsc85xx_config_intr()
2156 if (rc < 0) in vsc85xx_config_intr()
2170 if (irq_status < 0) { in vsc85xx_handle_interrupt()
2188 if (rc < 0) in vsc85xx_config_aneg()
2199 if (rc < 0) in vsc85xx_read_status()
2220 vsc8531->base_addr, 0); in vsc8514_probe()
2249 vsc8531->base_addr, 0); in vsc8574_probe()
2316 if (rate_magic < 0) in vsc85xx_probe()
2343 .phy_id_mask = 0xfffffff0,
2367 .phy_id_mask = 0xfffffff0,
2391 .phy_id_mask = 0xfffffff0,
2416 .phy_id_mask = 0xfffffff0,
2439 .phy_id_mask = 0xfffffff0,
2463 .phy_id_mask = 0xfffffff0,
2487 .phy_id_mask = 0xfffffff0,
2511 .phy_id_mask = 0xfffffff0,
2535 .phy_id_mask = 0xfffffff0,
2559 .phy_id_mask = 0xfffffff0,
2581 .phy_id_mask = 0xfffffff0,
2606 .phy_id_mask = 0xfffffff0,
2631 .phy_id_mask = 0xfffffff0,
2654 .phy_id_mask = 0xfffffff0,
2677 .phy_id_mask = 0xfffffff0,